MT8976 Mitel Networks Corporation, MT8976 Datasheet - Page 17

• Manufacturer Part Number: MT8976
• Description: ISO-CMOS ST-BUS FAMILY T1/ESF Framer Circuit
• Manufacturer: Mitel Networks Corporation

compatible equipment (see ANSI T1.102 and AT & T
Technical Advisory #34). On the receive side the
bipolar
format by the line receiver circuit. The resulting
split phase signals are input at the RxA and RxB pins
on the MT8976. The signals are combined together
to produce a composite return to zero signal, which
is clocked into the device at RxD. An uncommitted
nand gate in the MT8940/41 can be used for this
purpose.
The MT8976 can be interfaced to a high speed
parallel bus or to a microprocessor using the
MT8920B Parallel Access Circuit (STPA). Figure 11
shows the MT8976 interfaced to a parallel bus
structure using two STPA‘s operating in modes 1 and
2.
The first STPA operating in mode 2 (MMS=0,
MS1=1, 24/32=0),
information between the parallel telecom bus and the
T1 or CEPT link via DSTi and DSTo. The second
STPA, operating in mode 1 (MMS = 1 ) provides
access from the signalling and link control bus to the
MT8976 status and control channels. All signalling
and link functions may be controlled easily through
SIGNALLING
CONTROL
PARALLEL
TELECOM
SPEED
LINK
BUS
HIGH
BUS
and
line signal is converted
A
R/W
OE
routes
D
CS
A
CS
R/W
DTACK
IRQ
lACK
DS
Figure 11 - Using the MT8976 in a Parallel Bus Environment
D
MMS MS1 24/32
0
0
0
0
-A
-D
-A
-D
5
MT8920B
(Mode 2)
5
7
MT8920B
(Mode 1)
7
+5V
MMS
+5V
data
STo0
STo1
STo0
STo1
STi0
STi0
C4i
C4i
F0i
F0i
into a unipolar
and/or
•
•
•
voice
DSTi
DSTo
CSTi0
CSTo
CSTi1
F0i
E1.5i
C2i
C1.5i
Extractor
MT8976
Clock
the STPA transmit RAM’s Tx0, Tx1,
information is read at receive RAM Rx0. In addition,
interrupts can be set up to notify the system in case
of slips, loss of sync, alarms, violations, etc.
Mitel also manufactures a thick film hybrid device,
the MH89760/760B, which incorporates the line
driver, receiver and clock extractor circuitry.
second SIP hybrid, the MH89761, provides the
necessary equalization circuitry to condition the
signal for transmission up to 655 feet over 22 AWG
twisted pair.
Note: the configurations shown in Figures 10 and 11
using the MT8940/41 may not meet specific jitter
performance requirements.
PLL or line interface unit with transmit jitter
attenuator may be required for applications designed
to meet specific standards.
E8Ko
RxD
TxA
RxA
RxB
TxB
•
•
•
Receiver
Driver
1.544
Line
MHz
Line
Rx
Tx
•
ISO-CMOS
F0i
CVb
C2o
F0b
C4b
C8Kb
MT8940/
MT8941
AAAA AAAA
AA AA
AAAA
AA AA
AA AA
AA AA
AA AA
AA AA
AA AA
AAAAAAAAAAAAAAAAAAAAAA
AAAA AAAA
A more sophisticated
MT8940/41
AAAA AAAA
12.355/12.352
16.388/16.384
AAAA AAAA
MH89761
SWITCH
EQU
MHz Osc.
DIP
MHz Osc.
AAAA AA AA
MT8976
while status
A
A A
A A
A A
A A
A A
A A
4-45
A