MT8976 Mitel Networks Corporation, MT8976 Datasheet - Page 14

• Manufacturer Part Number: MT8976
• Description: ISO-CMOS ST-BUS FAMILY T1/ESF Framer Circuit
• Manufacturer: Mitel Networks Corporation

MT8976
pointer and the ST-BUS read pointer will begin to
decrease over time. When this delay approaches the
minimum two channel threshold, the buffer will
perform a controlled slip, which will reset the internal
ST-BUS read pointers so that there is exactly 34
channels delay between the two pointers. This will
result
information output in the previous frame. Repetition
of up to one DS1 frame of information is possible.
Conversely, if the data on the DS1 side is being
written into the buffer at a rate faster than that at
which it is being read out on the ST-BUS side, the
delay between the DS1 frame and the ST-BUS frame
will increase over time. A controlled slip will be
performed when the throughput delay exceeds 42
ST-BUS channels. This slip will reset the internal ST-
BUS counters so that there is a 10 channel delay
between the DS1 write pointer and the ST-BUS read
4-42
* Note: Only when in ESF mode and CRC
option is enabled.
in
some
ISO-CMOS
Candidate
Candidate
ST-BUS
New Frame Position
Hunt Mode
channels
In sync
Candidate
Figure 8 - Off-Line Framer State Diagram
Verify
False
Candidate
containing
Candidate
False Candidate
Check
CRC
Valid Candidate
False
Candidate
Receiver
Resync
pointer, resulting in loss of up to one frame of
received DS1 data.
Note that when the device performs a controlled slip,
the ST-BUS address pointers are repositioned so
that there is either a 10 channel or a 34 channel
delay between the input DS1 frame and the output
ST-BUS
controlled slip only if the delay exceeds 42 channels
or is less than 2 channels, there is an 8 channel
hysteresis built into the slip mechanism. The device
can, therefore, absorb 8 channels or 32.5µs of jitter
in the received signal.
There is no loss of frame sync, multiframe sync or
any errors in the signalling bits when the device
performs a slip. The information on the FDL pins in
ESF or SLC-96 mode will, however, undergo slips at
the same time.
*
Out of
Sync.
frame.
Maintenance
Forced
Reframe
Since
the
Valid Candidate
buffer
performs
a