ISL96017 Intersil Corporation, ISL96017 Datasheet - Page 5

• Manufacturer Part Number: ISL96017
• Description: 128-Tap DCP / 16kbit EEPROM and I2C Serial Interface
• Manufacturer: Intersil Corporation

I
Electrical Specifications
NOTES:
10. RDNL = (R
12.
13. t
14. Parameter is not 100% tested.
11. RINL = [R
2
2. Typical values are for T
3. LSB = (V(RW)
4. FSerror = (V(RW)
5. ZSerror = V(RW)
6. DNL = [(V(RW)
7. INL = [V(RW)
8.
9. MI = (R
C Timing Diagram
SYMBOL
t
TC
7F hex, respectively.
TC
valid STOP condition at the end of a Write sequence of a I
write cycle.
t
t
HD:STO
WC
(OUTPUT TIMING)
SU:WP
HD:WP
(INPUT TIMING)
Rpu
t
Cb
DH
t
t
V
R
R
F
is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a
=
=
0
---------------------------------------------------------------------------------------------- -
(
--------------------------------------------------------------- -
[
– R
Max V RW
Max Ri
[
[
Max V RW
i
Max Ri
i
– (MI * i) – R
SDA
127
SCL
– R
STOP Condition Hold Time
Output Data Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL
SDA and SCL Bus Pull-Up Resistor
Off-Chip
WP Setup Time
WP Hold Time
SDA
(
(
127
i
– i * LSB – V(RW)
t
(
(
)/127. MI is minimum increment. R
i
SU:STA
(
0
– V(RW)
i-1
)
127
(
– V(RW)
/LSB
+
) Min Ri
)/MI – 1, for i from 1 to 111. i is the DCP Register setting.
–
Min Ri
)i
– VDD)/LSB
)i
)
A
PARAMETER
+
127
) Min V RW
(
= 25°C and V
–
(
i-1
Min V RW
0
)/127. V(RW)
]/MI, for i from 1 to 111.
)
)/LSB] – 1, for i from 1 to 127. i is the DCP Register setting.
] 2 ⁄
5
)
Over recommended operating conditions unless otherwise stated. All voltages with respect to GND. (Continued)
(
]
(
t
HD:STA
(
×
0
]/LSB, for I = 1 to 127.
(
1
------------------ -
125°C
×
)i
10
DD
t
)i
)
F
) 2 ⁄
127
)
6
]
= 3.3V.
t
; for i = 1 to 111, and T = -40°C to 85°C
SU:DAT
×
and V(RW)
---------------- -
125°C
10
0
From SDA rising edge to SCL falling edge. Both
crossing 70% of VDD
From SCL falling edge crossing 30% of VDD,
until SDA enters the 30% to 70% of VDD
window
Total on-chip and off-chip
Maximum is determined by t
For Cb = 400pF, max is about 2~2.5kΩ
For Cb = 40pF, max is about 15~20kΩ
Before START condition
After STOP condition
6
From 30% to 70% of VDD
From 70% to 30% of VDD
and R
for i = 16 to 111, and T = -40°C to 85°C
0
t
HIGH
127
are the voltage at pin RW for the DCP Register set to 7F hex and 00 hex respectively.
2
C serial interface Write operation, to the end of the self-timed internal non-volatile
are the resistances between RH and RW with the DCP Register set to 00 hex and
ISL96017
TEST CONDITIONS
t
LOW
t
HD:DAT
R
and t
F
t
R
t
AA
t
DH
0.1*Cb
0.1*Cb
MIN
600
20+
20+
10
0
1
(Note 1)
TYP
t
BUF
t
MAX
SU:STO
250
250
400
600
600
April 17, 2006
UNIT
FN8243.1
kΩ
pF
ns
ns
ns
ns
ns
ns