ISL96017 Intersil Corporation, ISL96017 Datasheet - Page 9

• Manufacturer Part Number: ISL96017
• Description: 128-Tap DCP / 16kbit EEPROM and I2C Serial Interface
• Manufacturer: Intersil Corporation

Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, one or more
Data Bytes, and a STOP condition (See Figure 8). After each
of the bytes, this device responds with an ACK. At this time,
if the operation is only writing to volatile registers, then the
device enters its standby state. If one or more Data Bytes
are to be written to non-volatile memory, the device begins
its internal write cycle to non-volatile memory. During this
cycle, the device ignores transitions at the SDA and SCL
pins, and the SDA output is at a high impedance state. When
the internal non-volatile write cycle is completed, the device
enters its standby state.
The memory is organized as 128 pages of 16 bytes each.
This allows writing 16 bytes on a single I
operation, followed by a single internal non-volatile write
cycle. The addresses of bytes within a page share the same
eight MSBs, and differ on the four LSBs. For example, the
first page is located at addresses 0 hex through F hex, the
second page is located at addresses 10 hex through 1F hex,
etc.
A Write operation with more than one Data Byte sends the
first Data Byte to the memory address indicated by the three
address bits of the Identification Byte plus the eight bits of
the Address Byte, the second Data Byte to the following
address, etc.
A single Write operation has to stay within a page. If the
Address Byte corresponds to the lowest address of a page,
then the Write operation can have anywhere from 1 to 16
Data Bytes. If the Address Byte corresponds to the highest
address of a page, then only one byte can be written with
that Write operation.
See “Access to DCP Register and IVR” for additional
information.
Data Protection
The WP pin has to be at logic HIGH to perform any Write
operation to the device. When WP is active (LOW) the
device ignores Data Bytes of a Write operation, does not
SCL FROM MASTER
SDA OUTPUT FROM
SDA OUTPUT FROM
TRANSMITTER
RECEIVER
9
START
FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER
2
HIGH IMPEDANCE
C interface
1
ISL96017
respond to them with ACK, and instead, goes to its standby
state waiting for a new START condition.
A valid Identification Byte, Address Byte, and total number of
SCL pulses act as a protection of both volatile and non-
volatile registers.
During a Write sequence, Data Bytes are loaded into an
internal shift register as they are received. If the address bits
in the Identification Byte plus the bits in the Address Byte are
all ones, the Data Byte is transferred to the DCP Register at
the falling edge of the SCL pulse that loads the last bit (LSB)
of the Data Byte.
The STOP condition acts as a protection of non-volatile
memory. Non-volatile internal write cycles are started by
STOP conditions.
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 9). The master
initiates the operation issuing the following sequence: a
START, the Identification Byte with the R/W bit set to “0”, an
Address Byte which contains the LSBs of the memory
address, a second START, and a second Identification Byte
with the same address bits but with the R/W bit set to “1”.
After each of the three bytes, this device responds with an
ACK. Then this device transmits Data Bytes as long as the
master responds with an ACK during the SCL cycle following
the eighth bit of each byte. The master terminates the Read
operation (issuing a STOP condition) following the last bit of
the last Data Byte. The Data Bytes are from the memory
location indicated by an internal pointer. This pointer initial
value is determined by the address bits in the Identification
Byte plus the bits in the Address Byte in the Read operation
instruction, and increments by one during transmission of
each Data Byte.
8
HIGH IMPEDANCE
ACK
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April 17, 2006
FN8243.1