DS2154

Manufacturer Part NumberDS2154
DescriptionEnhanced E1 Single Chip Transceiver
ManufacturerDallas Semiconducotr
DS2154 datasheet
 


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FEATURES
Complete E1(CEPT) PCM-30/ISDN-PRI
transceiver functionality
Onboard long- and short-haul line interface for
clock/data recovery and waveshaping
32-bit or 128-bit crystal-less jitter attenuator
Generates line build outs for both 120 =and
75 =lines
Frames to FAS, CAS, and CRC4 formats
Dual onboard two-frame elastic store slip buffers
that can connect to asynchronous backplanes up to
8.192 MHz
8-bit parallel control port that can be used directly
on either multiplexed or non-multiplexed buses
Extracts and inserts CAS signaling
Detects and generates Remote and AIS alarms
Programmable output clocks for Fractional E1,
H0, and H12 applications
Fully independent transmit and receive
functionality
Full access to both Si and Sa bits aligned with
CRC multiframe
Four separate loopbacks for testing functions
Large counters for bipolar and code violations,
CRC4 codeword errors, FAS errors, and E bits
Pin compatible with DS2152 T1 Enhanced Single-
Chip Transceiver
5V supply; low power CMOS
2
100-pin 14mm
body LQFP package
DESCRIPTION
The DS2154 Enhanced Single-Chip Transceiver (ESCT) contains all of the necessary functions for
connection to E1 lines. The device is an upward compatible version of the DS2153 Single-Chip
Transceiver. The onboard clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ
serial stream. The DS2154 automatically adjusts to E1 22AWG (0.6 mm) twisted-pair cables from 0 to
over 2 km in length. The device can generate the necessary G.703 waveshapes for both 75-ohm coax and
120-ohm twisted cables. The onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be
placed in either the transmit or receive data paths. The framer locates the frame and multiframe
boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling
data, Si, and Sa bit information. The device contains a set of internal registers which the user can access
to control the operation of the unit. Quick access via the parallel control port allows a single controller to
handle many E1 lines. The device fully meets all of the latest E1 specifications including ITU G.703,
G.704, G.706, G.823, G.932, and I.431 as well as ETS 300 011, 300 233, 300 166, TBR 12 and TBR 13.
Enhanced E1 Single Chip Transceiver
PACKAGE OUTLINE
1
ORDERING INFORMATION
DS2154L
DS2154LN
1 of 87
DS2154
(0°C to 70°C)
(-40°C to +85°C)
112099

DS2154 Summary of contents

  • Page 1

    ... E1 lines. The device is an upward compatible version of the DS2153 Single-Chip Transceiver. The onboard clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ serial stream. The DS2154 automatically adjusts to E1 22AWG (0.6 mm) twisted-pair cables from 0 to over length. The device can generate the necessary G.703 waveshapes for both 75-ohm coax and 120-ohm twisted cables ...

  • Page 2

    ... Hardware Based Signaling............................................................................................................ 49 8.0 PER-CHANNEL CODE GENERATION ........................................................................ 51 Transmit Side Code Generation.................................................................................................... 51 Receive Side Code Generation ..................................................................................................... 53 9.0 CLOCK BLOCKING REGISTERS ................................................................................ 54 10.0 ELASTIC STORES OPERATION ................................................................................. 56 11.0 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION .............................. 57 Hardware Scheme ......................................................................................................................... 57 Internal Register Scheme Based on Double-Frame ...................................................................... 57 Internal Register Scheme Based on CRC4 Multiframe ................................................................ 60 TABLE OF CONTENTS DS2154 ...

  • Page 3

    ... LINE INTERFACE FUNCTIONS ................................................................................... 62 Receive Clock and Data Recovery................................................................................................ 62 Transmit Waveshaping and Line Driving..................................................................................... 63 Jitter Attenuator............................................................................................................................. 64 13.0 TIMING DIAGRAMS...................................................................................................... 67 Synchronization Flowchart ........................................................................................................... 72 Transmit Data Flow Diagram ....................................................................................................... 73 14.0 CHARACTERISTICS .................................................................................................... 74 Absolute Maximum Rating........................................................................................................... 74 DC Parameters .............................................................................................................................. 74 AC Parameters .............................................................................................................................. 75 Timing........................................................................................................................................... 77 Package Description...................................................................................................................... DS2154 ...

  • Page 4

    ... INTRODUCTION The DS2154 is a super-set version of the popular DS2153 E1 Single-Chip Transceiver offering the new features listed below. All of the original features of the DS2153 have been retained and software created for the original devices is transferable into the DS2154. Option for non-multiplexed bus operation ...

  • Page 5

    ... DS2154 ENHANCED E1 SINGLE-CHIP TRANSCEIVER Figure 1 DS2154 ...

  • Page 6

    ... The analog AMI/HDB3 waveform off of the E1 line is transformer coupled into the RRING and RTIP pins of the DS2154. The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing/multiframe pattern ...

  • Page 7

    ... Master Clock Input. O Quartz Crystal Driver Connect. - Receive Analog Signal Ground. O Interrupt Connect Connect Connect. O Transmit Analog Tip Output. - Transmit Analog Signal Ground. - Transmit Analog Positive Supply. O Transmit Analog Ring Output. O Transmit Channel Block. O Transmit Link Clock. I Transmit Link Data DESCRIPTION DS2154 ...

  • Page 8

    ... Data Bus Bit 6 / Address/Data Bus Bit 6. Data Bus Bit 7 / Address/Data Bus Bit 7. I Address Bus Bit 0. I Address Bus Bit 1. I Address Bus Bit 2. I Address Bus Bit 3. I Address Bus Bit 4. I Address Bus Bit 5. I Address Bus Bit DS2154 ...

  • Page 9

    ... Receive Negative Data Output. O Receive Positive Data Output. O Receive Channel Clock. O Receive Signaling Freeze Output. O Receive Signaling Output. O Receive Serial Data. O Receive Multiframe Sync. O Receive Frame Sync. I/O Receive Sync. O Receive Loss of Sync / Loss Of Transmit Clock. I Receive System Clock DESCRIPTION DS2154 ...

  • Page 10

    ... DS2154 PIN DESCRIPTION Table 1-2 TRANSMIT SIDE DIGITAL PINS Transmit Clock [TCLK]. A 2.048 MHz primary clock. Used to clock data through the transmit side formatter. Must be present for the parallel control port to operate properly. If not present, the Loss Of Transmit Clock (LOTC) function can provide a clock. ...

  • Page 11

    ... See Section 9 for details. Receive Serial Data [RSER]. Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled DS2154 ...

  • Page 12

    ... Receive Carrier Loss [RCL]. Set high when the line interface detects a loss of carrier. [Note: a test mode exists to allow the DS2154 to detect carrier loss at RPOSI and RNEGI in place of detection at RTIP and RRING]. Receive Signaling Freeze [RSIGF]. Set high when the signaling data is frozen via either automatic or manual intervention ...

  • Page 13

    ... Quartz Crystal Driver [XTALD]. A quartz crystal of 2.048 MHz may be applied across MCLK and XTALD instead of a TTL level clock source at MCLK. Leave open circuited if a TTL clock source is applied at MCLK. ]). and are active low signals when MUX=11 DS2154 is active DS ...

  • Page 14

    ... Digital Signal Ground [DVSS]. 0.0 volts. Should be tied to the RVSS and TVSS pins. Receive Analog Signal Ground [RVSS]. 0.0 volts. Should be tied to the DVSS and TVSS pins. Transmit Analog Ground [TVSS]. 0.0 volts. Should be tied to the RVSS and DVSS pins. pins. When LIUC DS2154 tied high, the ...

  • Page 15

    ... DS2154 REGISTER MAP Table 1-3 ADDRESS R/W REGISTER NAME 00 R BPV or Code Violation Count BPV or Code Violation Count CRC4 Error Count 1 / FAS Error Count CRC4 Error Count E-Bit Count 1 / FAS Error Count E-Bit Count 2. 06 R/W Status 1. 07 R/W Status 2. ...

  • Page 16

    ... R/W Transmit Signaling 3. 43 R/W Transmit Signaling 4. 44 R/W Transmit Signaling 5. 45 R/W Transmit Signaling 6. 46 R/W Transmit Signaling 7. 47 R/W Transmit Signaling 8. REGISTER ABBREVIATION DS2154 TCBR2 TCBR3 TCBR4 TIR1 TIR2 TIR3 TIR4 TIDR RCBR1 RCBR2 RCBR3 RCBR4 RAF RS1 RS2 RS3 RS4 RS5 RS6 RS7 ...

  • Page 17

    ... R/W Transmit Channel 8. 68 R/W Transmit Channel 9. 69 R/W Transmit Channel 10. 6A R/W Transmit Channel 11. 6B R/W Transmit Channel 12. 6C R/W Transmit Channel 13. REGISTER ABBREVIATION DS2154 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16 TSiAF TSiNAF TRA TSa4 TSa5 TSa6 TSa7 TSa8 RSiAF RSiNAF RRA RSa4 ...

  • Page 18

    ... R/W Receive Channel 13. 8D R/W Receive Channel 14. 8E R/W Receive Channel 15. 8F R/W Receive Channel 16. 90 R/W Receive Channel 17. 91 R/W Receive Channel 18. REGISTER ABBREVIATION DS2154 TC14 TC15 TC16 TC17 TC18 TC19 TC20 TC21 TC22 TC23 TC24 TC25 TC26 TC27 TC28 TC29 TC30 TC31 TC32 RC1 ...

  • Page 19

    ... Test Registers 1, 2, and 3 are used only by the factory; these registers must be cleared (set to all 0s) on power-up initialization to insure proper operation. 2. Register banks Bxh, Cxh, Dxh, Exh, and Fxh are not accessible. REGISTER ABBREVIATION TEST3 (set to 00h DS2154 RC19 RC20 RC21 RC22 RC23 ...

  • Page 20

    ... ID register at address 0FH and the user can read the MSB to determine which chip is present since in the DS2154 the MSB will be set and in the DS2152 it will be set The lower 4 bits of the IDR are used to display the die revision of the chip. ...

  • Page 21

    ... FAS received in error 3 consecutive times 1=resync if FAS or bit 2 of non-FAS is received in error 3 consecutive times Sync Enable. 0=auto resync enabled 1=auto resync disabled Resync. When toggled from low to high, a resync is initiated DS2154 (LSB) ID2 ID1 ID0 (LSB) FRC SYNCE RESYNC ...

  • Page 22

    ... Three consecutive incorrect FAS received Alternate (RCR1.2=1) the above criteria is met or three consecutive incorrect bit 2 of non- FAS received 915 or more CRC4 code words out of 1000 received in error Two consecutive MF alignment words received in error DS2154 ITU SPEC. G.706 4.1.1 4.1.2 G.706 4.2 and 4.3.2 G.732 5.2 ...

  • Page 23

    ... RLCLK low during Sa4 bit position. See Section 13 for timing details. Receive Side Backplane Clock Select. 0=if RSYSCLK is 1.544 MHz 1=if RSYSCLK is 2.048 MHz Receive Side Elastic Store Enable. 0=elastic store is bypassed 1=elastic store is enabled Not Assigned. Should be set to 0 when written DS2154 (LSB) RESE - ...

  • Page 24

    ... Transmit Signaling All 1s. 0=normal operation 1=force timeslot 16 in every frame to all 1s TSYNC Mode Select. 0=frame mode (see the timing in Section 13) 1=CAS and CRC4 multiframe mode (see the timing in Section 13) TSYNC I/O Select. 0=TSYNC is an input 1=TSYNC is an output DS2154 (LSB) TSM TSIO ...

  • Page 25

    ... TPOSO and TNEGO are one full TCLKO period wide 1=pulses at TPOSO and TNEGO are 1/2 TCLKO period wide Automatic E-Bit Enable. 0=E-bits not automatically set in the transmit direction 1=E-bits automatically set in the transmit direction Function of RLOS/LOTC Pin. 0=Receive Loss of Sync (RLOS) 1=Loss of Transmit Clock (LOTC DS2154 (LSB) AEBE PF ...

  • Page 26

    ... Receive HDB3 Enable. 0=HDB3 disabled 1=HDB3 enabled Receive G.802 Enable. See Section 13 for details. 0=do not force RCHBLK high during bit 1 of timeslot 26 1=force RCHBLK high during bit 1 of timeslot 26 Receive CRC4 Enable. 0=CRC4 disabled 1=CRC4 enabled DS2154 (LSB) RG802 RCRC4 ...

  • Page 27

    ... FRAMER LOOPBACK When CCR1.7 is set the DS2154 will enter a Framer LoopBack (FLB) mode. See Figure 1-1 for more details. This loopback is useful in testing and debugging applications. In FLB, the DS2154 will loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur: 1 ...

  • Page 28

    ... AUTOMATIC ALARM GENERATION When either CCR2.4 or CCR2.5 is set to 1, the DS2154 monitors the receive side to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all 1s) reception, or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the DS2154 will either force an AIS alarm (if CCR2 ...

  • Page 29

    ... TSIG pin into the data stream presented at the TSER pin Transmit Side Backplane Clock Select. 0=if TSYSCLK is 1.544 MHz 1=if TSYSCLK is 2.048 MHz Receive Carrier Loss (RCL) Alternate Criteria. 0=RCL declared upon 255 consecutive 0s (125 us) 1=RCL declared upon 2048 consecutive DS2154 (LSB) TBCS RCLA ...

  • Page 30

    ... Next, the LIRST (CCR5.7) bit should be toggled from reset the line interface circuitry (it will take the DS2154 about recover from the LIRST bit being toggled). Finally, after the RSYSCLK and TSYSCLK inputs are stable, the ESR bit should be toggled from and then back to 0 (this step can be skipped if the elastic stores are not being used) ...

  • Page 31

    ... Please see Figure 1-1 for more details. LOCAL LOOPBACK When CCR4.6 is set the DS2154 will be forced into Local LoopBack (LLB). In this loopback, data will continue to be transmitted as normal through the transmit side of the DS2154. Data being received at RTIP and RRING will be replaced with the data being transmitted ...

  • Page 32

    ... STATUS AND INFORMATION REGISTERS There is a set of four registers that contain information on the current real time status of the DS2154, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer Status Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers will be set ...

  • Page 33

    ... CRC Resync Criteria Met. Set when 915/1000 code words are received in error. FAS Resync Criteria Met. Set when 3 consecutive FAS words are received in error. CAS Resync Criteria Met. Set when 2 consecutive CAS MF alignment words are received in error DS2154 (LSB) FASRC CASRC ...

  • Page 34

    ... FAS Sync Active. Set while the synchronizer is searching for alignment at the FAS level. CAS MF Sync Active. Set while the synchronizer is searching for the CAS MF alignment word. CRC4 MF Sync Active. Set while the synchronizer is searching for the CRC4 MF alignment word DS2154 (LSB) CASSA CRC4SA ...

  • Page 35

    ... CRC4 mode (CCR1.0=0). This counter is useful for determining the amount of time the DS2154 has been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400 ms, then the search should be abandoned and proper action taken ...

  • Page 36

    ... MF more than two 0s in two frames (512 bits) bit 3 of non-align frame set to 0 for three consecutive occasions in 255-bit times, at least 32 1s are received DS2154 ITU SPEC. G.732 4.2 G.732 5.2 O.162 2.1.5 O.162 1.6.1.2 O.162 2 ...

  • Page 37

    ... LOTC pin high if enabled via TCR2.0. Receive CRC4 Multiframe. Set on CRC4 multiframe boundaries; will continue to be set every arbitrary boundary if CRC4 is disabled. Transmit Elastic Store Slip. Set when the elastic store has either repeated or deleted a frame of data DS2154 (LSB) RCMF TSLIP ...

  • Page 38

    ... Receive Elastic Store Slip Occurrence. 0=interrupt masked 1=interrupt enabled Receive Unframed All 1s. 0=interrupt masked 1=interrupt enabled Receive Remote Alarm. 0=interrupt masked 1=interrupt enabled Receive Carrier Loss. 0=interrupt masked 1=interrupt enabled Receive Loss of Sync. 0=interrupt masked 1=interrupt enabled DS2154 (LSB) RCL RLOS ...

  • Page 39

    ... Timer. 0=interrupt masked 1=interrupt enabled Transmit Align Frame. 0=interrupt masked 1=interrupt enabled Loss Of Transmit Clock. 0=interrupt masked 1=interrupt enabled Receive CRC4 Multiframe. 0=interrupt masked 1=interrupt enabled Transmit Side Elastic Store Slip Occurrence. 0=interrupt masked 1=interrupt enabled DS2154 (LSB) RCMF TSLIP ...

  • Page 40

    ... ERROR COUNT REGISTERS There are a set of four counters in the DS2154 that record bipolar or code violations, errors in the CRC4 SMF code words, E bits as reported by the far end, and word errors in the FAS. Each of these four counters are automatically updated on either 1-second boundaries (CCR2.7=0) or every 62.5 ms (CCR2 ...

  • Page 41

    ... MSB of the 10-bit CRC4 error count. LSB of the 10-bit CRC4 error count. (note 1) (note 1) (note 1) EB4 EB3 EB2 NAME AND DESCRIPTION MSB of the 10-bit E-Bit count. LSB of the 10-bit E-Bit count DS2154 (LSB) CRC9 CRC8 CRCCR1 CRC1 CRC0 CRCCR2 (LSB) EB9 EB8 EBCR1 ...

  • Page 42

    ... The lower 2 bits of FASCR2 at address 04 are the most significant bits of the 10-bit E-bit counter. FAS8 FAS7 FAS6 FAS2 FAS1 FAS0 NAME AND DESCRIPTION MSB of the 12-bit FAS error count. LSB of the 12-bit FAS error count DS2154 (LSB) (note 2) (note 2) FASCR1 (note 1) (note 1) FASCR2 ...

  • Page 43

    ... DS0 MONITORING FUNCTION The DS2154 has the ability to monitor one DS0 64 kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which channel monitored by properly setting the TCM0 to TCM4 bits in the CCR4 register. In the receive direction, the RCM0 to RCM4 bits in the CCR5 register need to be properly set ...

  • Page 44

    ... DS0 channel data will appear in the RDS0M register. Receive Channel Monitor Bit 3. Receive Channel Monitor Bit 2. Receive Channel Monitor Bit 1. Receive Channel Monitor Bit 0. LSB of the channel decode that determines which receive DS0 channel data will appear DS2154 (LSB (LSB) RCM2 RCM1 ...

  • Page 45

    ... Receive DS0 Channel Bit 7. Receive DS0 Channel Bit 6. Receive DS0 Channel Bit 5. Receive DS0 Channel Bit 4. Receive DS0 Channel Bit 3. Receive DS0 Channel Bit 2. Receive DS0 Channel Bit 1. LSB of the DS0 channel (last bit to be received DS2154 (LSB ...

  • Page 46

    ... PROCESSOR-BASED SIGNALING The Channel Associated Signaling (CAS) bits embedded in the E1 stream can be extracted from the receive stream and inserted into the transmit stream by the DS2154. Each of the 30 voice channels has four signaling bits (A/B/C/D) associated with it. The numbers in parenthesis () are the voice channel associated with a particular signaling bit ...

  • Page 47

    ... D(3) A(18) B(18) D(4) A(19) B(19) D(5) A(20) B(20) D(6) A(21) B(21) D(7) A(22) B(22) D(8) A(23) B(23) D(9) A(24) B(24) D(10) A(25) B(25) D(11) A(26) B(26) D(12) A(27) B(27) D(13) A(28) B(28) D(14) A(29) B(29) D(15) A(30) B(30) NAME AND DESCRIPTION Spare Bits. Remote Alarm Bit. Signaling Bit A for Channel 1. Signaling Bit D for Channel 30 DS2154 pin to toggle low upon INT (LSB TS1 (40) C(16) D(16) TS2 (41) C(17) D(17) TS3 (42) C(18) D(18) TS4 (43) C(19) D(19) TS5 (44) C(20) D(20) TS6 (45) C(21) D(21) TS7 (46) C(22) D(22) TS8 (47) C(23) D(23) TS9 (48) C(24) D(24) TS10 (49) C(25) D(25) TS11 (4A) C(26) D(26) TS12 (4B) C(27) D(27) TS13 (4C) C(28) D(28) TS14 (4D) ...

  • Page 48

    ... Each Transmit Signaling Register (TS1 to TS16) contains the CAS bits for two timeslots that will be inserted into the outgoing stream if enabled via TCR1.5. On multiframe boundaries, the DS2154 will load the values present in the Transmit Signaling Register into an outgoing signaling shift register that is internal to the device ...

  • Page 49

    ... Transmit Side Via the THSE control bit (CCR3.2), the DS2154 can be set up to take the signaling data presented at the TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The hardware signaling insertion capabilities of the DS2154 are available whether the transmit side elastic store is enabled or disabled ...

  • Page 50

    ... Channel 5 signaling data from TS6) CH3 CH18 CH2 CH7 CH22 CH6 CH11 CH26 CH10 CH15 CH30 CH14 TCBR3=04h (source voice Channel 10 signaling data from TS11) TCBR4=00h DS2154 (LSB) CH17* CH1* TCBR1(22) CH21 CH5 TCBR2(23) CH25 CH9 TCBR3(24) CH29 CH13 TCBR4(25) ...

  • Page 51

    ... TRANSMIT SIDE CODE GENERATION In the transmit direction there are two methods by which channel data from the backplane can be overwritten with data generated by the DS2154. The first method which is covered in Section 8.1.1 was a feature contained in the original DS2153 while the second method which is covered in Section 8.1 new feature of the DS2154 ...

  • Page 52

    ... TIDR3 NAME AND DESCRIPTION MSB of the Idle Code (this bit is transmitted first) LSB of the Idle Code (this bit is transmitted last NAME AND DESCRIPTION MSB of the Code (this bit is transmitted first DS2154 (LSB) CH2 CH1 TIR1 (26) CH10 CH9 TIR2 (27) CH18 ...

  • Page 53

    ... TC32 register into the transmit data stream NAME AND DESCRIPTION MSB of the Code (this bit is sent first to the backplane) LSB of the Code (this bit is sent last to the backplane DS2154 (LSB) CH2 CH1 TCC1 (A0) CH10 CH9 TCC2 (A1) CH18 ...

  • Page 54

    ... RC1 register into the receive data stream Receive Channel 32 Code Insertion Control Bit 0=do not insert data from the RC32 register into the receive data stream 1=insert data from the RC32 register into the receive data stream DS2154 (LSB) CH2 CH1 RCC1 (A4) CH10 ...

  • Page 55

    ... TCHBLK pin to remain low during this channel time 1=force the TCHBLK pin high during this channel time CH3 CH18 CH2 CH7 CH22 CH6 CH11 CH26 CH10 CH15 CH30 CH14 DS2154 (LSB) CH2 CH1 RCBR1 (2B) CH10 CH9 RCBR2 (2C) CH18 CH17 RCBR3 (2D) CH26 CH25 RCBR4 (2E) (LSB) CH2 ...

  • Page 56

    ... ELASTIC STORES OPERATION The DS2154 contains dual two-frame (512 bits) elastic stores, one for the receive direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can be used to rate-convert the E1 data stream to 1.544 Mbps (or a multiple of 1.544 Mbps) which is the T1 rate. Secondly, they can be used to absorb the differences in frequency and phase between the E1 data stream and an asynchronous (i ...

  • Page 57

    ... ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION The DS2154 provides for access to both the Sa and the Si bits via three different methods. The first is via a hardware scheme using the RLINK/RLCLK and TLINK/ TLCLK pins. The first method is discussed in Section 11.1. The second involves using the internal RAF/RNAF and TAF/TNAF registers and is discussed in Section 11 ...

  • Page 58

    ... Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. A Sa4 Sa5 NAME AND DESCRIPTION International Bit. Frame Non-Alignment Signal Bit. Remote Alarm. Additional Bit 4. Additional Bit 5. Additional Bit 6. Additional Bit 7. Additional Bit DS2154 (LSB (LSB) Sa6 Sa7 Sa8 ...

  • Page 59

    ... TAF: TRANSMIT ALIGN FRAME REGISTER (Address=20 Hex) (MSB [Must be programmed with the 7-bit FAS word; the DS2154 does not automatically set these bits] SYMBOL POSITION Si TAF.7 0 TAF.6 0 TAF.5 1 TAF.4 1 TAF.3 0 TAF.2 1 TAF.1 1 TAF.0 TNAF: TRANSMIT NON-ALIGN FRAME REGISTER (Address=21 Hex) ...

  • Page 60

    ... The 8 Si bits to be inserted into the non-align frame The 8 settings of remote alarm (RA) The 8 Sa4 settings in each CRC4 multiframe The 8 Sa5 settings in each CRC4 multiframe The 8 Sa6 settings in each CRC4 multiframe The 8 Sa7 settings in each CRC4 multiframe The 8 Sa8 settings in each CRC4 multiframe DS2154 ...

  • Page 61

    ... TSa7 register into the transmit data stream Additional Bit 8 Insertion Control Bit. 0=do not insert data from the TSa8 register into the transmit data stream 1=insert data from the TSa8 register into the transmit data stream DS2154 (LSB) Sa6 Sa7 Sa8 ...

  • Page 62

    ... The DS2154 contains a digital clock recovery system. See the DS2154 Block Diagram in Section 1 and Figure 12-1 for more details. The DS2154 couples to the receive E1 shielded twisted pair or COAX via a 1:1 transformer. See Table 12-3 for transformer details. The 2.048 MHz clock attached at the MCLK pin is internally multiplied by 16 via an internal PLL and fed to the clock recovery system ...

  • Page 63

    ... This oversampling technique offers outstanding jitter tolerance (see Figure 12- 2 DS2154 ...

  • Page 64

    ... This LBO is not recommended for use in the A2 revision of the DS2154. Due to the nature of the design of the transmitter in the DS2154, very little jitter (less then 0.005 UIpp broadband from 100 kHz) is added to the jitter present on TCLK. Also, the waveforms that they create are independent of the duty cycle of TCLK ...

  • Page 65

    ... JITTER ATTENUATOR The DS2154 contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications. ...

  • Page 66

    ... DS2154 JITTER TOLERANCE Figure 12-2 DS2154 TRANSMIT WAVEFORM TEMPLATE Figure 12 DS2154 ...

  • Page 67

    ... DS2154 JITTER ATTENUATION Figure 12 DS2154 ...

  • Page 68

    ... RSYNC in the frame mode (RCR1.6=0). 2. RSYNC in the multiframe mode (RCR1.6=1). 3. RLCLK is programmed to pulse high during the Sa4 bit position. 4. RLINK will always output all 5 Sa bits as well as the rest of the receive data stream. 5. This diagram assumes the CAS MF begins with the FAS word DS2154 ...

  • Page 69

    ... Data from the E1 Channels 13, 17, 21, 25, and 29 is dropped (Channel 2 from the E1 link is mapped to Channel 1 of the T1 link, etc.) and the F-bit position is added (forced to 1). 2. RSYNC is in the output mode (RCR1.5=0). 3. RSYNC is in the input mode (RCR1.5=1). 4. RCHBLK is programmed to block Channel 24 DS2154 ...

  • Page 70

    ... RSIG normally contains the CAS multiframe alignment nibble (0000) in Channel 1. TRANSMIT SIDE TIMING Figure 13-5 NOTES: 1. TSYNC in the frame mode (TCR1.1=0). 2. TSYNC in the multiframe mode (TCR1.1=1). 3. TLINK is programmed to source only the Sa4 bit. 4. This diagram assumes both the CAS MF and the CRC4 begin with the align frame DS2154 ...

  • Page 71

    ... The signaling data at TSIG during Channel 1 is normally overwritten in the transmit formatter with the CAS multiframe alignment nibble (0000). 6. Shown is a non-align frame boundary. TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING (WITH ELASTIC STORE ENABLED) Figure 13-7 NOTES: 1. TCHBLK is programmed to block Channel 23. 2. The F-bit position is ignored by the DS2154 DS2154 ...

  • Page 72

    ... TRANSMIT SIDE 2.048 MHz (WITH ELASTIC STORE ENABLED) Figure 13-8 NOTE: 1. TCHBLK is programmed to block Channel 31. G.802 TIMING Figure 13-9 NOTE: 1. RCHBLK or TCHBLK is programmed to pulse high during timeslots 25, and during bit 1 of timeslot 26 DS2154 ...

  • Page 73

    ... DS2154 SYNCHRONIZATION FLOWCHART Figure 13- DS2154 ...

  • Page 74

    ... DS2154 TRANSMIT DATA FLOW Figure 13-11 NOTES: 1. TCLK Should be tied to RCLK and TSYNC should be tied to RFSYNC for data to be properly sourced from RSER. 2. Auto Remote Alarm if enabled will only overwrite bit 3 of timeslot 0 in the Non Align Frames if the alarm needs to be sent. ...

  • Page 75

    ... RECOMMENDED DC OPERATING CONDITIONS PARAMETER Logic 1 Logic 0 Supply CAPACITANCE PARAMETER Input Capacitance Output Capacitance DC CHARACTERISTICS PARAMETER Supply Current @ 5V Input Leakage Output Leakage Output Current (2.4V for DS2154L; - +85 C for DS2154LN) SYMBOL MIN TYP 4.75 DD SYMBOL MIN ...

  • Page 76

    ... Output Current (0.4V) NOTES: 1. Applies to RVDD, TVDD, and DVDD. 2. TCLK=RCLK=TSYSCLK=RSYSCLK=2.048 MHz; outputs open circuited. 3. 0.0V < V < Applied to when 3-stated. INT I +4 DS2154 mA ...

  • Page 77

    ... DHR t 0 DHW t 15 ASL t 10 AHL ASD PW 30 ASH ASED DDR t 50 DSW DS2154 =5V =5% for DS2154L; DD =5V =5% for DS2154LN) DD TYP MAX UNITS NOTES ...

  • Page 78

    ... RCHBLK, RMSYNC, RSYNC See Figures 14-4 to 14-6 for details. NOTES: 1. Jitter attenuator enabled in the receive path. 2. Jitter attenuator disabled or enabled in the transmit path. 3. RSYSCLK=1.544 MHz. 4. RSYSCLK=2.048 MHz. =5V =5% for DS2154L =5V =5% for DS2154LN SYMBOL MIN ...

  • Page 79

    ... INTEL BUS READ AC TIMING (BTS=0/MUX=1) Figure 14-1 INTEL BUS WRITE AC TIMING (BTS=0/MUX=1) Figure 14 DS2154 ...

  • Page 80

    ... MOTOROLA BUS AC TIMING (BTS=1/MUX=1) Figure 14-3 RECEIVE SIDE AC TIMING Figure 14-4 NOTES: 1. RSYNC is in the output mode (RCR1.5=0). 2. RLCLK will only pulse high during Sa bit locations as defined in RCR2; no relationship between RLCLK and RSYNC or RFSYNC is implied DS2154 ...

  • Page 81

    ... Valid Delay TCLK to TESO Valid Delay TCLK to TCHBLK, TCHBLK, TSYNC, TLCLK Delay TSYSCLK to TCHCLK, TCHBLK See Figures 14-7 to 14-9 for details. NOTES: 1. TSYSCLK=1.544 MHz. 2. TSYSCLK=2.048 MHz. =5V =5% for DS2154L =5V =5% for DS2154LN SYMBOL MIN TYP t ...

  • Page 82

    ... RECEIVE SYSTEM SIDE AC TIMING Figure 14-5 NOTES: 1. RSYNC is in the output mode (RCR1.5=0). 2. RSYNC is in the input mode (RCR1.5=1). RECEIVE LINE INTERFACE AC TIMING Figure 14 DS2154 ...

  • Page 83

    ... TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled. 4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled. 5. TLINK is only sampled during Sa bit locations as defined in TCR2; no relationship between TLCLK/TLINK and TSYNC is implied DS2154 ...

  • Page 84

    ... TRANSMIT SYSTEM SIDE AC TIMING Figure 14-8 NOTES: 1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. 2. TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic store is enabled. TRANSMIT LINE INTERFACE SIDE AC TIMING Figure 14 DS2154 ...

  • Page 85

    ... INTEL BUS READ AC TIMING (BTS=0/MUX=0) Figure 14 SYMBOL MIN DS2154 =5V =5% for DS2154T; DD =5V =5% for DS2154TN) DD TYP MAX UNITS NOTES ...

  • Page 86

    ... INTEL BUS WRITE AC TIMING (BTS=0/MUX=0) Figure 14-11 MOTOROLA BUS READ AC TIMING (BTS=1/MUX=0) Figure 14-12 MOTOROLA BUS WRITE AC TIMING (BTS=1/MUX=0) Figure 14- DS2154 ...

  • Page 87

    ... DS2154 100-PIN LQFP PKG 100-PIN DIM MIN MAX A - 1. 1.35 1.45 B 0.17 0.27 C 0.09 0.20 D 15.80 16.20 D1 14.00 BSC E 15.80 16.20 E1 14.00 BSC e 0.50 BSC L 0.45 0.75 DETAIL DS2154 ...