DS2154 Dallas Semiconducotr, DS2154 Datasheet - Page 30

• Manufacturer Part Number: DS2154
• Description: Enhanced E1 Single Chip Transceiver
• Manufacturer: Dallas Semiconducotr

POWER-UP SEQUENCE
On power-up, after the supplies are stable, the DS2154 should be configured for operation by writing to
all of the internal registers (this includes the Test Registers) since the contents of the internal registers
cannot be predicted on power-up. Next, the LIRST (CCR5.7) bit should be toggled from 0 to 1 to reset
the line interface circuitry (it will take the DS2154 about 40 ms to recover from the LIRST bit being
toggled). Finally, after the RSYSCLK and TSYSCLK inputs are stable, the ESR bit should be toggled
from a 0 to a 1 and then back to 0 (this step can be skipped if the elastic stores are not being used). Both
TCLK and RCLKI must be present for the parallel control port to operate properly.
CCR4: COMMON CONTROL REGISTER 4 (Address=A8 Hex)
(MSB)
RLB
SYMBOL
TCM4
TCM3
TCM2
TCM1
TCM0
LIAIS
RLB
LLB
LLB
POSITION
CCR4.7
CCR4.6
CCR4.5
CCR4.4
CCR4.3
CCR4.2
CCR4.1
CCR4.0
LIAIS
NAME AND DESCRIPTION
Remote Loopback.
0=loopback disabled
1= loopback enabled
Local Loopback.
0=loopback disabled
1=loopback enabled
Line Interface AIS Generation Enable. See Figure 1-1 for
details.
0=allow normal data from TPOSI/TNEGI to be transmitted at
TTIP and TRING
1=force unframed all 1s to be transmitted at TTIP and TRING
Transmit Channel Monitor Bit 4. MSB of a channel decode
that determines which transmit channel data will appear in the
TDS0M register. See Section 6 for details.
Transmit Channel Monitor Bit 3.
Transmit Channel Monitor Bit 2.
Transmit Channel Monitor Bit 1.
Transmit Channel Monitor Bit 0. LSB of the channel decode.
TCM4
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TCM3
TCM2
TCM1
TCM0
(LSB)
DS2154