RTL8181 ETC, RTL8181 Datasheet
RTL8181
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RTL8181 Summary of contents
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... RTL8181 Wireless LAN Access Point/Gateway Controller DATA SHEET ISSUE 4: June 10, 2003 ...
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... Modify some register definitions and function descriptions. Issue 4 1.0 3. Add package information. 4. Remove 32 bits flash interface support 5. Add pin definitions for Maxim RF interface CONFIDENTIAL Details of Change 2 RTL8181 Originator Issue Date David Hsu 11/29/2002 David Hsu 12/9/2002 Victor Hsu 03/03/2003 Victor/David 2003/06/10 ...
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... Table of Contents 1. OVERVIEW ................................................................................................................................... 4 2. PIN DESCRIPTION 3. ADDRESS MAPPING 4. REGISTER MAPPING 5. SYSTEM CONFIGURATION 6. INTERRUPT CONTROLLER 7. MEMORY CONTROLLER 8. ETHERNET CONTROLLER 9. UART CONTROLLER 10. TIMER & WATCHDOG 11. GPIO CONTROL 12. 802.11B WLAN CONTROLLER 13. PACKAGE INFORMATION CONFIDENTIAL ................................................................................................................. 5 ........................................................................................................... 12 ......................................................................................................... 13 .......................................................................................... 16 ........................................................................................ 17 ............................................................................................... 18 .......................................................................................... 21 ......................................................................................................... 30 ................................................................................................... 33 ................................................................................................................... 35 ................................................................................. 37 ......................................................................................... 48 3 RTL8181 v1.0 ...
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... GPIO Flash SDRAM The embedded processor of RTL8181 is Lexra LX5280 32bit RISC CPU, with 8K separate instruction and data caches. A protection unit (MMU) allows the memory be segmented and protected, and this unit is required in the modern operation system (e.g., Linux). The processor pipeline is a dual - issues and 6 stage architecture. The dual - issue CPU fetches two instructions per cycle, and which could allow two instructions are executed concurrently in two pipes via some instructions ...
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... Memory Interface MD[31-0] I/O 198,197,195 P1,P2,N3,N ,194,193,19 2,N1,M3,M 2,191,190,1 2,M1,L2,L3, 88,187,185, L1,K2,K3,K 184,182,181 1,J2,J1,H2, ,180,179,17 H1,G2,F1,G 7,176,174,1 3,F2,E1,F3, 73,171,170, E2,D1,D2,E 169,168,166 3,A1,B1,B2, ,165,163,16 C3 2,161,160,1 59,158 MA[21-0]/ O 115,116,118 B14,A15,D1 DQM[3-0] ,119,121,12 4,C14,A14, 2,124,125,1 C13,B13,C1 27,128,130, 2,A12,C11, 131,133,134 B11,C10,A1 ,135,136,13 1,B10,A10, CONFIDENTIAL Data for SDRAM, Flash. Address for SDRAM, Flash. MA[15-18] mapping to DQM[3-0] for SDRAM 5 RTL8181 v1.0 ...
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... I/O power 3.3V (Digital), I/O 3.3V GND (Digital) Core logic power 1.8V (Digital) Core logic 1.8Ground (Digital) Wireless LAN power 3.3V(Analog) Wireless LAN Ground (Analog), GA7 VSUB Core logic 1.8V power(Digital) Core logic LAN Ground(Digital) Core logic power 1.8V(Digital) Core logic 1.8V GND WLAN Tx/Rx traffic indicator or JTAG reset. 6 RTL8181 v1.0 ...
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... Bus Data: Serial data output, with resistive dividers on board to allow programming from +5V levels. 3-wire Bus Enable: Enable serial port output, with resistive dividers on board to allow programming from +5V levels. Not used in the RFMD RF chipset. Not used in the RFMD RF chipset. RF2494 Gain Select: Digital output. 7 RTL8181 v1.0 ...
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... Antenna Select -: The antenna selects signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. This is a complement for ANTSEL+ for differential drive of antenna switches. Transmit and Receive Switch Control: This is a complement for TRSW-. 1:TX 0:RX 8 RTL8181 v1.0 ...
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... Antenna Select -: The antenna selects signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. This is a complement for ANTSEL+ for differential drive of antenna switches. Not used in the Maxim RF chipset. Not used in the Maxim RF chipset. Output Pin as VCO VCC Power Enable/Disable. 9 RTL8181 v1.0 ...
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... Interrupt A: Used to request an interrupt asserted low when an interrupt condition occurs, as defined by the Interrupt Status, Interrupt Mask. Initiator Ready: This indicates the initiating agent’s ability to complete the current data phase of the transaction bus master, this signal will be asserted low when the RTL8181 is ready to 10 RTL8181 v1.0 ...
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... Management Data Input/Output: This pin provides the bi-directional signal used to transfer management information. General purpose I/O pins group B pins ICFG[5-4] power on latch =[1-0]. GPIO[5-2] mapping to JTAG_TDO(JTAG test data output),JTAG_TRSTN(JTAG reset),JTAG_TMS(JTAG test mode select),JTAG_TDI(JTAG test data input). General purpose I/O pins group B pin 15 to 12. 11 RTL8181 v1.0 ...
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... Address Mapping The RTL8181 supports gigabytes of address space. The memory map of RTL8181 is managed by MMU, which will translate the virtual address to physical address. The memory is segmented into four regions by its access mode and caching capability as shown in following table. ...
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... None cacheable region 0xbfff_ffff The memory map of RTL8181 I/O devices and registers are located in KSEG1 segment (uncacheable region). The following table illustrates the address map: Virtual address range Size (bytes) Mapped device 0xBD01_0000 – 0xBD01_0FFF 4K 0xBD01_1000 – 0xBD01_1FFF 4K 0xBD20_0000 – 0xBD2F_FFFF 1M 0xBD30_0000 – ...
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... Ethernet 0 Type filter1 register Ethernet 0 Type filter2 register Ethernet 0 Type filter3 register Ethernet0 MII access register Ethernet0 control register 2 Ethernet0 unicast address register Ethernet0 mismatch packet counter Ethernet0 transmit collision counter Ethernet0 receive error count Ethernet1 control register 0 Ethernet1 ID Ethernet1 multicast register 14 RTL8181 v1.0 ...
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... WLAN beacon interrupt interval register WLAN PHY configuration register WLAN default key 0 register WLAN default key 1 register WLAN default key 2 register WLAN default key 3 register WLAN configuration register 5 WLAN transmit priority polling register WLAN contention window register WLAN receive descriptor start address register 15 RTL8181 v1.0 ...
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... PLLMN_R EG 0xBD01_0108 1 MEM_REG RTL8181 Memory clock rate 0xBD01_0109 1 CPU_REG RTL8181 CPU clock rate Bridge Control Register (BRIDGE_REG) Since the Lexra bus clock rate is fast than the network device, it needs a bus bridge between the CPU and device (i.e., Ethernet and Wireless LAN controller). Also, this bridge is existed between CPU and PCI bridge. ...
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... CPUDIVEN Enable CPUDIV writw,0 disable ,1 enable 7-4 Reserved - 6. Interrupt Controller RTL8181 provides six hardware- interrupt inputs IRQ0-IRQ5 internally. Some devices will share the same IRQ signal. Following table displays the IRQ map used by devices: IRQ Number Interrupt Source 0 Timer/Counter interrupt 1 GPIO/LBC interrupt ...
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... Memory Controller RTL8181 provides a memory control module that could access external asynchronous SDRAM and flash memory. RTL8181 could interface to PC100 or PC133-compliant SDRAM, and supports with auto-refresh mode, which requires 4096-cycle refresh in 64 ms. The SDRAM could be accessed in two banks (CS0#, and CS1#), and its size and timing are configurable in register ...
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... Besides, RTL8181could also supports two banks (F_CS0# and F_CS1#) access for flash memory. The system will always boot up from bank 0. The boot bank is mapped to KSEG1 and its beginning physical address at 0xBFC0_0000 (physical address: 0x1FC0_0000). Bank 1 flash memory will be mapped to the address “0x1FC0_000 + flash size”. The flash size is configurable from bytes for each bank ...
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... T_RFC timing parameter for refresh interval Basic unit, 1*clock cycle “0000” means 1 unit (1 clock cycle) Note: The clock cycle is based memory clock. The SDRAM timing: The write access timing of flash memory: A[20..0] F_CE0# OE# Tcs WR# D[n..0] CONFIDENTIAL Twp Twp 20 RTL8181 R/W 111 R/W 11111 R/W 11111 v1.0 ...
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... D[n..0] 8. Ethernet Controller There are two 10/100M Ethernet MAC embedded in RTL8181. The Ethernet device has bus master capability, which will move packets between SDRAM and Ethernet controller through DMA mechanism. Thus, it could offload the CPU loading and get better performance. Besides, it also supports full-duplex operation, making possible 200Mbps bandwidth at no additional cost ...
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... It rolls over when becomes full cleared to zero by read command. Receive error count. This 16-bit R counter increments by 1 for each valid packet received . It is cleared to zero by read command. R/W InitVal R/W 000 R/W 000 R R/W 0 R/W 0 R R RTL8181 v1.0 ...
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... The formula for the inter frame gap is 011: 9.6us/ 960ns 100: 9.6+4*0.1us/ 960+4*10ns 101: 9.6+8*0.1us/ 960+8*10ns 110: 9.6+12*0.1us/ 960+12*10ns 111: 9.6+16*0.1us/ 960+16*10ns CONFIDENTIAL W R/W 00 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W InitVal R R/W 1111 R/W 011 23 RTL8181 v1.0 ...
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... Rx FIFO overflow interrupt pending Write “1” to clear the interrupt.. 3 RDUIP Rx descriptor unavailable interrupt pending. Set when the Rx Descriptors have been exhausted. Write “1” to clear the interrupt and it also trigger CONFIDENTIAL R/W 0 Total retries = 16 + (TXRR * 16) R/W InitVal R/W 0 R/W InitVal R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W InitVal R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R RTL8181 v1.0 ...
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... DplxCtrl, SpdCtrl, and FlCtrl bits. 1: forced mode (disable N-way). The software may force MII operating mode by writing the corresponding value to the DplxCtrl, LinkCtrl, SpdCtrl,FlCtrl bits. CONFIDENTIAL R/W 0 R/W 0 R/W InitVal R/W 0 R/W 0x01 R/W 0 R/W 1 R RTL8181 v1.0 ...
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... A command bit. TCP checksum offload enable. Driver sets this bit to ask NIC to offload TCP checksum. CONFIDENTIAL Frame_Length VLAN_TAG TX_BUFFER_ADDRESS Dummy 26 RTL8181 R Offset 0 Offset 4 Offset 8 Offset 12 v1.0 ...
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... TES Transmit Error Summary. When set, indicates that at least one of the following errors occurred: OWC, EXC, LNKF. This bit is valid only when LS (Last segment bit) is set. CONFIDENTIAL 8 7 CC3-0 Frame_Length VLAN_TAG TX_BUFFER_ADDRESS Dummy 27 RTL8181 Offset 0 Offset 4 Offset 8 Offset 12 v1.0 ...
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... Rx descriptor ring. Once NIC’ s internal receive descriptor pointer reaches here, it will return to the first descriptor of Rx descriptor ring after this descriptor is used by packet reception. CONFIDENTIAL 8 7 Buffer_Size T VLAN_TAG RX_BUFFER_ADDRESS Dummy 28 RTL8181 Offset 0 Offset 4 Offset 8 Offset 12 v1.0 ...
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... Broadcast Address Received. When set, indicates that a broadcast packet is received. BAR and MAR will not be set simultaneously. CONFIDENTIAL Frame_Length VLAN_TAG V A RX_BUFFER_ADDRESS Dummy 29 RTL8181 Offset 0 Offset 4 Offset 8 Offset 12 v1.0 ...
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... Logic Address of receive buffer. 9. UART Controller RTL8181 provides a 16C550 compatible UART, which contains 16 byte FIFOs. In addition, auto flow control is provided, in which, auto-CTS mode (CTS controls transmitter) and auto-RTS mode (Receiver FIFO contents and threshold control RTS) are both supported. The baud rate is programmable and allows division of any input reference clock (2^16-1) and generates an internal 16x clock ...
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... No characters have been Read RBR removed from or input to FIFO during the last character times and at 1 character in it. THRE bit set. Reading IIR or write THR CTS#,DSR#,RI#,DCD# Reading MSR R RTL8181 R/W R/W R/W InitVal InitVal 110 0 000 0 InitVal ...
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... DR Data ready. Character mode: data ready in RBR FIFO mode: receiver FIFO is not empty. Modem Status Register (UART_MSR) Bit Bit Name Description CONFIDENTIAL R/W InitVal R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 11 R/W InitVal R/W 0 R/W 0 R/W 0 R/W InitVal R/W InitVal 32 RTL8181 v1.0 ...
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... R R Description Timer/Counter control register Timer/Counter interrupt register Clock division base register time-out duration. time-out duration. time-out duration. time-out duration. Timer/Counter 0 count register Timer/Counter 1 count register Timer/Counter 2 count register Timer/Counter 3 count register R/W R/W R/W R/W R/W R/W 33 RTL8181 Access R/W R/W R/W R/W R/W R/W R/W R InitVal InitVal InitVal ...
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... The divided factor of clock source. If DivFactor is N, the watchdag timer divide by N+1.This value could not timer mode or watchdog. The clock source is 22MHz. Watchdog Control Register (WDTCNR) CONFIDENTIAL R/W InitVal R/W R/W InitVal R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W InitVal R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W InitVal R RTL8181 v1.0 ...
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... GPIO Control RTL8181 provides two sets of GPIO pins – PortA and PortB . PortA has 16 pins and PortB has 16 pins. Every GPIO pin can be configured as input or output pins via register PA(B)DIR. Register PA(B)DATA could be used to control the signals (high or low) of GPIO pins ...
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... PB12IM[1:0 PortB.12 interrupt mode ] 00 = disable interrupt 01 = enable falling edge interrupt 10 = enable rising edge interrupt 11 = enable both falling or rising edge interrupt 27-26 PB13IM[1:0 PortB.13 interrupt mode ] 00 = disable interrupt CONFIDENTIAL R/W 00 R/W 00 R/W 00 R/W 00 R/W 00 R/W 00 R/W 00 R/W 00 R/W 00 R/W 00 R RTL8181 v1.0 ...
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... RTL8181 integrates with a wireless LAN MAC and a direct sequence spread spectrum baseband processor, and is full compliance with IEEE 802.11 and IEEE 802.11b specifications. RTL8181 has on board A/D and D/A converters for analog I and Q inputs and outputs. Differential phase shift keying modulation schemes DBPSK and DQPSK, with data scrambling capability, are available along with complementary code keying to provide a variety of data rates ...
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... TSF timer register (WLAN_TSFTR) Bit Bit Name Description 63-0 TSFT Timing Synchronization Function Timer: RTL8181 maintain a TSF timer with modules 2^64 counting in increments of microseconds. The 8 octets are the timestamp field of beacon and probe response frame. Basic Rate Set Register (WLAN_BRSR) Bit Bit Name ...
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... Reserved 4 RST Reset: Setting this bit to 1 forces the RTL8181 do the WLAN MAC reset. During reset reset state, it will disable the transmitter and receiver, and reinitializes the FIFOs. The values of WLAN_IDR and WLAN_MAR7 will have no changes. This bit is 1 during the reset operation, and is cleared to 0 when the reset operation is complete ...
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... TLPDOK Transmit Low Priority Descriptor OK: Indicates that a packet of low priority descriptor exchange sequence has been successfully completed. 1 RER Receive Error: Indicates that a packet has a CRC32 or ICV error. 0 ROK Receive OK: In normal mode, indicates the successful completion of a packet reception. CONFIDENTIAL 40 RTL8181 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ...
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... CWMIN Contention Window minimum value: Set indicate that Cwmin=8. Set indicate that Cwmin=32. 30 SEQGEN Sequence number generation switch. 0 – Enabled. Sequence number is generated by RTL8181. 1 – Disabled. Sequence number should be filled by software. 29-25 - Reserved 24 SAT Set ACK Timeout: The EIFS, ACK and CTS timeouts are derived from the following ...
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... Reserved 23 CBSSID Check BSSID, To DS, From DS Match Packet: When set to 1, the RTL8181 will check the Rx data type frame’s BSSID and From DS fields, according to NETYPE (bits 3:2, MSR), to determine set to Link Infrastructure or Adhoc network. 22 APWRMGT Accept Power Management Packet: This bit will determine whether the RTL8181 will accept or reject packets with the power management bit set ...
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... Bit Name Description 7-6 EEM These 2 bits select the operating mode. 00: Operating in network/host communication mode. 11: Before writing to the WLAN_CONFIG0 and 3 registers, the RTL8181 must be placed in this mode. This will prevent accidental change of the configurations of the WLAN controller. 5-0 - Reserved Configuration Register 0 (WLAN_CONFIG0) ...
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... Normal working state. This is the power-on default value. 4-2 - Reserved 1-0 RFTYPE Radio Front End Programming Method: The combination of these two bits indicate what kind of the RF module is being used with the RTL8181. 11: Philips, 10: RFMD, 01: Intersil Security Configuration Register (WLAN_SCR) Bit Bit Name Description 7-6 ...
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... WEP key, which the when KM is set to WEP40, and the 64 most significant bits (bits 103:40) will be reserved. This register is only permitted to read/write by 4-byte access. Default Key 2 Register (WLAN_DK2) Bit Bit Name Description 127:104 - Reserved 103:0 DK2 Default Key 2: These 104 bits (bits 103:0) indicate the default 104-bit WEP key, which the CONFIDENTIAL 45 RTL8181 R/W - R/W R/W R/W R/W R/W R/W R/W R/W - R/W R/W ...
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... Writing to this bit has no effect. 6 HPQ High Priority Queue Polling: Write this bit by software to notify the RTL8181 that there is a high priority packet(s) waiting to be transmitted. The RTL8181 will clear this bit automatically after all high priority packets have been transmitted. ...
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... DMA mechanism of the Normal Priority Queue. This bit is invalid when DPS (bit3, Config 2) is set SLPQ Stop Low Priority Queue: Write this bit by software to notify the RTL8181 to stop the DMA mechanism of the Low Priority Queue. Contention Window Register (WLAN_CWR) Bit ...
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... The receive FIFO is controlled by the FIFO threshold value in RXFTH. This value determines the number of long words written into the FIFO from the MAC unit before a DMA req uest for system memory occurs. Once the RTL8181 gets the bus, it will continue to transfer the long words from the FIFO until the data in the FIFO is less than one long word, or has reached the end of the packet, or the max DMA burst size is reached MXDMA ...
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... Millimeter 0.30 4.General appearance spec. should be based 0.26 on final visual inspection spec. TITLE : 208L QFP ( 28x28 mm**2 ) FOOTPRINT 2.6mm 28.25 PACKAGE OUTLINE DRAWING 28.25 LEADFRAME MATERIAL: 0.80 APPROVE 31.50 31.50 0.75 CHECK 1.55 - 0.10 REALTEK SEMI-CONDUCTOR CO., LTD - 12 ° 49 RTL8181 DOC. NO. 530-ASS-P004 VERSION 1 PAGE DWG NO. Q208 - 1 DATE APR. 11.1997 v1.0 ...
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... REFERENCE DOCUMENT : JEDEC MO-205. 6. THE PATTERN OF PIN 1 FIDUCIAL IS FOR REFERENCE ONLY. 0.598 --- 0.598 --- 0.031 --- TITLE : 292LD TFBGA ( 17x17mm) PACKAGE OUTLINE 0.004 0.004 SUBSTRATE MATERIAL: BT RESIN 0.005 APPR. 0.006 ENG. 0.003 QM. 20/20 CHK. DWG. REALTEK SEMI-CONDUCTOR CO., LTD 50 RTL8181 DWG NO.. Rev NO PRODUCT CODE DATE. SHT No. v1.0 ...