RTL8181 ETC, RTL8181 Datasheet - Page 37

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

www.DataSheet4U.com
29-28
31-30
Port B Interrupt Status Register (PBISR)
Bit
15-0
12. 802.11b WLAN Controller
RTL8181 integrates with a wireless LAN MAC and a direct sequence spread spectrum baseband processor, and is full
compliance with IEEE 802.11 and IEEE 802.11b specifications.
RTL8181 has on board A/D and D/A converters for analog I and Q inputs and outputs. Differential phase shift keying
modulation schemes DBPSK and DQPSK, with data scrambling capability, are available along with complementary code
keying to provide a variety of data rates. Both receive and transmit AGC functions obtain maximum performance in the analog
portions of the transceiver. It also includes a built- in enhanced signal detector to alleviate severe multi-path effects. The target
environment for 11Mbps is 125ns RMS delay spread. It also supports short preamble and antenna diversity. For security issues,
RTL8181 has implemented a high performance internal WEP engine supporting up to 104-bits WEP.
The WLAN controller is a DMA bus-master device, and uses descriptor-based buffer structure for packet transmission and
reception. These features will definitely offload much CPU loading.
RTL818 provides various interfaces for external RF module. Currently, it could interface with the RF modules as Intersil,
RFMD and Philip.
WLAN Controller register Set
Virtual Address Size
0xBD40_0000
0xBD 40_0008
0xBD40_0018
0xBD40_0020
0xBD40_0024
0xBD40_0028
0xBD40_002C
0xBD40_002E
0xBD40_0037
0xBD40_003C
0xBD40_003E
0xBD40_0040
0xBD40_0044
0xBD40_0048
CONFIDENTIAL
PB14IM[1:0
]
PB15IM[1:0
]
Bit Name
PBIP[15:0] Interrupt pending status. Self clear after read.
(byte)
8
8
8
4
4
4
4
6
1
2
2
4
4
4
01 = enable falling edge interrupt
10 = enable rising edge interrupt
11 = enable both falling or rising edge interrupt
PortB.14 interrupt mode
00 = disable interrupt
01 = enable falling edge interrupt
10 = enable rising edge interrupt
11 = enable both falling or rising edge interrupt
PortB.15 interrupt mode
00 = disable interrupt
01 = enable falling edge interrupt
10 = enable rising edge interrupt
11 = enable both falling or rising edge interrupt
Description
Name
WLAN_ID
WLAN_MAR
WLAN_TSFTR
WLAN_TLPDA
WLAN_TNPDA
WLAN_THPDA
WLAN_BRSR
WLAN_BSSID
WLAN_CR
WLAN_IMR
WLAN_ISR
WLAN_TCR
WLAN_RCR
WLAN_TINT
Description
ID Register : The ID register is only permitted to write by 4-byte
access. Read access can be byte, word, or double word access.
Multicast Register: The MAR register is only permitted to write by
4-bye access. Read access can be byte, word, or double word
access.
Timing Synchronization Function Timer Register
Transmit Low Priority Descriptors Start Address (32-bit).
(256-byte alignment)
Transmit Normal Priority Descriptors Start Address (32-bit).
(256-byte alignment)
Transmit High Priority Descriptors Start Address (32-bit).
(256-byte alignment)
Basic Rate Set Register
Basic Service Set ID
Command Register
Interrupt Mask Register
Interrupt Status Register
Transmit (Tx) Configuration Register
Receive (Rx) Configuration Register
Timer Interrupt Register. Once having written a nonzero value to
37
R/W
R/W
R/W
R
00
00
InitVal
00
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RTL8181
v1.0