RTL8181 ETC, RTL8181 Datasheet - Page 11

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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TRDYB
PAR
STOPB
RSTB
MII Interface
LTXC,
WTXC
LTXEN,
WTXEN
LTXD[3-0]
, WTXD
[3-0]
LRXC,
WRXC
LCOL,
WCOL
LRXDV,
WRXDV
LRXD[3-0
],
WRXD[3-
0]
LRXER,
WRXER
LMDC,
WMDC
LMDIO,
WMDIO
GPIO
GPIOB[11-
0]
GPIOB[15
-12]
CONFIDENTIAL
S/T/
S
T/S *X
S/T/
S
O
I
O
O
I
I
I
I
I
O
I/O 41,19
I/O 205,206,207,
I/O 200,201,202,
51,29
60,38
43,44
50,49,47,46
27,26,24,23
44,22
40,18
2,3,5,6,8,9,1
1,12,13
203
*X
*X
*X
53,31
59,37
57,56,55,54
35,34,33,32
J19
R2
B16
B15
Y20
W11
T17
V18,V17,W
19,W18
V12,Y13,W
12,Y12
W17,V11
U18,V13
W16,W9
V15,V16,Y
18,Y17,Y11
,W10,V10,
Y10
V14,V9
W15,W8
Y16,Y9
U1,U2,U3,
W1,Y1,Y2,
W4,V5,Y4,
W5,V6,Y5
R1,T1,T2,T
3
complete the current data phase transaction. This signal is used in conjunction
with the TRDYB signal. Data transaction takes place at the rising edge of CLK
when both IRDYB and TRDYB are asserted low. As a target, this signal indicates
that the master has put data on the bus.
Target Ready: This indicates the target agent’s ability to complete the current
phase of the transaction.
As a bus master, this signal indicates that the target is ready for the data during
write operations and with the data during read operations. As a target, this signal
will be asserted low when the (slave) device is ready to complete the current data
phase transaction. This signal is used in conjunction with the IRDYB signal. Data
transaction takes place at the rising edge of CLK when both IRDYB and TRDYB
are asserted low.
Parity: This signal indicates even parity across AD31-0 and C/BE3-0 including
the PAR pin. PAR is stable and valid one clock after each address phase. For data
phase, PAR is stable and valid one clock after either IRDYB is asserted on a
write transaction or TRDYB is asserted on a read transaction. Once PAR is valid,
it remains valid until one clock after the completion of the current data phase. As
a bus master, PAR is asserted during address and write data phases. As a target,
PAR is asserted during read data phases.
Stop: Indicates that the current target is requesting the master to stop the current
transaction.
Reset: Active low signal to reset the PCI device.
TXC is a continuous clock that provides a timing reference for the transfer of
TXD[3:0], TXE. In MII mode, it uses the 25 MHz or 2.5 MHz supplied by the
external PMD device.
Indicates the presence of valid nibble data on TXD[3:0].
Four parallel transmit data lines which are driven synchronous t o the TXC for
transmission by the external physical layer chip.
This is a continuous clock that is recovered from the incoming data. MRXC is
25MHz in 100Mbps and 2.5Mhz in 10Mbs.
This signal is asserted high synchronously by the external physical unit upon
detection of a collision on the medium. It will remain asserted as long as the
collision condition persists.
Data valid is asserted by an external PHY when receive data is present on the
RXD[3:0] lines, and it is deasserted at the end of the packet. This signal is valid
on the rising of the RXC.
This is a group of 4 data signals aligned on nibble boundaries which are driven
synchronous to the RXC by the external physical unit
This pin is asserted to indicate that invalid symbol has been detected in 100Mbps
MII mode. This signal is synchronized to RXC and can be asserted for a
minimum of one receive clock.
Management Data Clock: This pin provides a clock synchronous to MDIO,
which may be asynchronous to the transmit TXC and receive RXC clocks.
Management Data Input/Output: This pin provides the bi-directional signal used
to transfer management information.
General purpose I/O pins group B pins 11 to 0. If ICFG[5-4] power on latch
=[1-0]. GPIO[5-2] mapping to JTAG_TDO(JTAG test data
output),JTAG_TRSTN(JTAG reset),JTAG_TMS(JTAG test mode
select),JTAG_TDI(JTAG test data input).
General purpose I/O pins group B pin 15 to 12.
11
RTL8181
v1.0