RTL8181 ETC, RTL8181 Datasheet - Page 17

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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23
26-24
27
30-28
31
DPLL M,N parameter Register (PLLMN_REG)
The DPLL clock rate is setting by this equation:
44MHz*(M+1)/(N+1)
Bit
4-0
7-5
13-8
14
31-15
Memory parameter Register (MEM _REG)
Bit
2-0
3
7-4
CPU parameter Register (CPU_REG)
Bit
2-0
3
7-4
6. Interrupt Controller
RTL8181 provides six hardware- interrupt inputs IRQ0-IRQ5 internally. Some devices will share the same IRQ signal.
Following table displays the IRQ map used by devices:
IRQ Number Interrupt Source
0
1
2
3
4
5
CONFIDENTIAL
DISPCIB
WLANCKR Bus clock to WLAN clock ratio. 000=1:1,001=
WLANCKRE
N
Reserved
DISWLANB Disable WLAN, 0 enabe WLAN,1 disable
Bit Name
NDIV
Reserved
MDIV
MNEN
Reserved
Bit Name
MEMDIV
MEMDIVEN Enable MEMDIV writw,0 disable ,1 enable
Reserved
Bit Name
CPUDIV
CPUDIVEN Enable CPUDIV writw,0 disable ,1 enable
Reserved
Timer/Counter interrupt
GPIO/LBC interrupt
WLAN interrupt
UART/PCI interrupt
Ethernet0 interrupt
Ethernet1 interrupt
Disable PCI bridge,0 enabe PCI bridge,1
disable PCI bridge
1:2,010=1:3,011=1:4,100=1:5,101=1:6,110=1:
7,111=1:8. The WLAN maximum clock is
40MHz.
WLANCKR write enable
-
WLAN
Description
DPLL N parameter
-
DPLL M parameter
MDIV and NDIV write enable,0 disable ,1
enable
-
Description
MEM clock ,000:DPLL/1, 001: DPLL/1.5,
010: DPLL/2,011:DPLL/2.5,
100:DPLL/3,101:DPLL/4, 110:DPLL/6,
111:DPLL/8
-
Description
CPU clock ,000:DPLL/1, 001: DPLL/1.5, 010:
DPLL/2,011:DPLL/2.5,
100:DPLL/3,101:DPLL/4, 110:DPLL/6,
111:DPLL/8
-
17
R/W
R/W
R/W
-
R/W
R/W
R/W
-
R/W
R/W
-
R/W
R/W
R/W
-
R/W
R/W
R/W
-
0
101
0
-
0
InitVal
00011
-
10011
0
0
InitVal
000
0
-
InitVal
000
0
-
RTL8181
v1.0