RTL8181 ETC, RTL8181 Datasheet - Page 22

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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0xBD30_0014
0xBD30_0018
0xBD30_0020
0xBD30_0024
0xBD30_0028
0xBD30_002C
0xBD30_0030
0xBD30_0034
0xBD30_0038
0xBD30_003C
0xBD30_0080
0xBD30_0084
0xBD30_008C
Ethernet Control Register 1 (ETH0_CNR1, ETH1_CNR1)
Bit
31-29
28-26
25
24
20
19
18
17
16
15
14
13
CONFIDENTIAL
Bit Name
RXBLEN
TXBLEN
FIFOAddrPtr
TDFN
RST
RE
TE
TxFCE
RxFCE
Reserved
RxVLAN
RxChkSum
4
4
2
2
4
4
4
4
4
4
3
2
2
Description
Rx Burst length on Lexra bus.
000 - 010 = 64 bytes
Tx Burst length on Lexra bus.
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
FIFO Address Pointer: (Realtek internal use only
to test FIFO SRAM)
0: Both Rx and Tx FIFO address pointers are
updated in ascending way from 0 and upwards.
The initial FIFO address pointer is 0.
1: Both Rx and Tx FIFO address pointers are
updated in descending way from 1FFh and
downwards. The initial FIFO address pointer is
1FFh.
Tx Descriptor Fetch Notify. Set this bit to notify
the NIC to fetch the Tx descriptors. The NIC will
clear this bit automatically after all packets have
been transmitted. Writing 0 to this bit has no
effect.
Reset. A soft reset which disable the transmitter
and receiver, re- initializes the FIFOs, and buffer
pointer to the initial value.
Receiver enable.
Transmitter enable.
Transmit flow control enable.
Receive flow control enable
Receive VLAN un-tagging enable
Receive checksum offload enable
ETH1_TSAD
ETH1_RSAD
ETH1_IMR
ETH1_ISR
ETH1_TMF0
ETH1_TMF1
ETH1_TMF2
ETH1_TMF3
ETH1_MII
ETH1_CNR2
ETH1_MPC
ETH1_TXCOL Transmit collision counter. This
ETH1_RXER
Transmit Starting Logic Address of
Descriptor
Receive Starting Logic Address of
Descriptor
Ethernet0 Interrupt Mask Register
Ethernet0 Interrupt Status Register
Type match filter 0 register
Type match filter 1 register
Type match filter 2 register
Type match filter 3 register
MII access register
NIC control register 2
Ind icates the number of packets
discarded due to rx FIFO overflow.
It is a 24-bit counter. It is cleared to
zero by read command.
16-bit counter increments by 1 for
every collision event. It rolls over
when becomes full. It is cleared to
zero by read command.
Receive error count. This 16-bit
counter increments by 1 for each
valid packet received . It is cleared
to zero by read command.
22
R/W InitVal
R/W 000
R/W 000
R/W 0
W
W
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
RTL8181
v1.0