RTL8181 ETC, RTL8181 Datasheet - Page 19

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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Besides, RTL8181could also supports two banks (F_CS0# and F_CS1#) access for flash memory. The system will always boot
up from bank 0. The boot bank is mapped to KSEG1 and its beginning physical address at 0xBFC0_0000 (physical address:
0x1FC0_0000). Bank 1 flash memory will be mapped to the address “0x1FC0_000 + flash size”. The flash size is configurable
from 1M to 8M bytes for each bank. If flash size set to 4M or 8M the 0xBFC0_0000 still map the first 4M bytes of flash.
There will have a new memory mapping from 0xBE00_0000. The 0xBE00_0000 mapped to the bank 0 byte 0.
Memory Conf iguration Register Set
Virtual address Size (byte) Name
0xBD01_1000
0xBD01_1004
0xBD01_1008
Note: These three registers should be accessed in double word.
Memory Configuration Register (MCR)
Memory Timing Configuration Register 0 (MTCR0)
Note: The clock cycle is based memory clock.
Memory Timing Configuration Register 1 (MTCR1)
CONFIDENTIAL
Bit
.31-30 FLSIZE
29-28
27
26-25
24-23
22-21
20
19
18-16
15-0
Bit
31-28
27-24
23-20
19-16
15-0
Bit
Bit Name
SDRSIZE
CAS
FLBK0BW
FLBK1BW
-
SDBUSWID
MCK2LCK
BUSCLK
Reserved
Bit Name
CE0T_CS
CE0T_WP
CE1T_CS
CE1T_WP
-
Bit Name
4
4
4
Description
Flash size respective to one bank (byte).
00: 1M, 01: 2M, 10: 4M, 11:8M
SDRAM size respective to one bank (bit).
00: 512Kx16x2, 01: 1Mx16x4, 10: 2Mx16x4, 11:Reserved
CAS Latency
0: Latency=2, 1: Latency=3
Flash bank 0 bus width.
01: 16 bit
Flash bank 1 bus width
00 11 10: reserved, 01: 16 bit
Reserved
SDRAM bus width
0: 16 bit, 1: 32 bit
Memory clock mode.Power on latch from GPIOB[13].1:Memory clock
is the same as CPU clock. 0:memory clock following the power on latch
from SYSCFG[3-0].
Bus Clock to control auto-refresh timing
000:200, 001:100, 010:50, 011:25, 100:12.5, 101:6.25
110: 3.125, 111: 1.5625 MHz
Must be set to bit value 00.
Description
The timing interval between F_CE0# to WR#
Basic unit, 2*clock cycle
“0000” means 1 unit (2 clock cycles)
The timing interval for WR# to be pulled-low
Basic unit, 2*clock cycle
“0000” means 1 unit (2 clock cycles)
The timing interval between F_CE1# to WR#
Basic unit, 2*clock cycle
“0000” means 1 unit (2 clock cycles)
The timing interval for WR# to be pulled-low
Basic unit, 2*clock cycle
“0000” means 1 unit (2 clock cycles)
Reserved
MCR
MTCR0
MTCR1
Description
Description
Memory Configuration Register
Memory Timing Configuration Register 0
Memory Timing Configuration Register 1
19
R/W
R/W
R/W
WR
R
W/R
W/R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
InitVal
11
01
0
01
1
0
000
00
InitVal
1111
1111
1111
1111
InitVal
RTL8181
v1.0