IDT72V3674L15PF IDT, Integrated Device Technology Inc, IDT72V3674L15PF Datasheet - Page 12

• Manufacturer Part Number: IDT72V3674L15PF
• Description: IC FIFO 16384X36 15NS 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3674L15PF

• Function: Asynchronous
• Memory Size: 576K (16K x 36)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Configuration: Dual
• Density: 576Kb
• Access Time (max): 10ns
• Word Size: 36b
• Organization: 8Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3674L15PF

TABLE 1 — FLAG PROGRAMMING
FWFT input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and
CLKB (for FIFO2) will select FWFT mode. This mode uses the Output Ready
function (ORA, ORB) to indicate whether or not there is valid data at the data
outputs (A0-A35 or B0-B35). It also uses the Input Ready function (IRA, IRB)
to indicate whether or not the FIFO memory has any free space for writing.
In the FWFT mode, the first word written to an empty FIFO goes directly to data
outputs, no read request necessary. Subsequent words must be accessed
by performing a formal read operation.
the desired timing mode must remain static throughout FIFO operation. Refer
to Figure 3 (Master Reset) for a First Word Fall Through select timing diagram.
PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS
offset values for the Almost-Empty and Almost-Full flags. The Port B Almost-
Empty flag (AEB) Offset register is labeled X1 and the Port A Almost-Empty
flag (AEA) Offset register is labeled X2. The Port A Almost-Full flag (AFA)
Offset register is labeled Y1 and the Port B Almost-Full flag (AFB) Offset register
is labeled Y2. The index of each register name corresponds to its FIFO number.
The offset registers can be loaded with preset values during the reset of a FIFO,
programmed in parallel using the FIFO’s Port A data inputs, or programmed
in serial using the Serial Data (SD) input (see Table 1).
and FWFT modes.
— PRESET VALUES
one of the five preset values listed in Table 1, the flag select inputs must be HIGH
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
3. When this method of parallel programming is selected, Port A will assume Non-Interspersed Parity.
4. When IP Mode is selected, only parallel programming of the offset values via Port A, can be performed and Port A will assume Interspersed Parity.
5. IF parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.
IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW on the BE/
Following Master Reset, the level applied to the BE/FWFT input to choose
Four registers in the IDT72V3654/72V3664/72V3674 are used to hold the
FS0/SD, FS1/SEN and FS2 function the same way in both IDT Standard
To load a FIFO’s Almost-Empty flag and Almost-Full flag Offset registers with
FS2
H
H
H
H
H
H
H
L
L
L
L
L
L
FS1/SEN
H
H
H
H
H
H
H
L
L
L
L
L
L
FS0/SD
H
H
H
H
H
H
H
H
L
L
L
L
L
MRS1
↑
↑
↑
↑
↑
↑
↑
↑
X
X
X
X
X
MRS2
↑
↑
↑
↑
↑
↑
↑
↑
X
X
X
X
X
TM
WITH BUS-MATCHING
Parallel programming via Port A
Serial programming via SD
X1 AND Y1 REGlSTERS
12
or LOW during a master reset. For example, to load the preset value of 64 into
X1 and Y1, FS0, FS1 and FS2 must be HIGH when FlFO1 reset (MRS1) returns
HIGH. Flag-offset registers associated with FIFO2 are loaded with one of the
preset values in the same way with FIFO2 Master Reset (MRS2), toggled
simultaneously with FIFO1 Master Reset (MRS1). For relevant preset value
loading timing diagram, see Figure 3.
Reset on both FlFOs simultaneously with FS2 HIGH or LOW, FS0 and FS1
LOW during the LOW-to-HIGH transition of MRS1 and MRS2. The state of FS2
at this point of reset will determine whether the parallel programming method
has Interspersed Parity or Non-Interspersed Parity. Refer to Table 1 for Flag
Programming Flag Offset setup . It is important to note that once parallel
programming has been selected during a Master Reset by holding both FS0
& FS1 LOW, these inputs must remain LOW during all subsequent FIFO
operation. They can only be toggled HIGH when future Master Resets are
performed and other programming methods are desired.
in RAM but load the Offset registers in the order Y1, X1, Y2, X2. For Non-
Interspersed Parity mode the Port A data inputs used by the Offset registers are
(A10-A0), (A11-A0), or (A12-A0) for the IDT72V3654, IDT72V3664, or
IDT72V3674, respectively. For Interspersed Parity mode the Port A data inputs
used by the Offset registers are (A11-A9, A7-A0), (A12-A9, A7-A0), or (A13-
A9, A7-A0) for the IDT72V3654, IDT72V3664, or IDT72V3674, respectively.
The highest numbered input is used as the most significant bit of the binary
number in each case. Valid programming values for the registers range from
1 to 2,044 for the IDT72V3654; 1 to 4,092 for the IDT72V3664; and 1 to 8,188
for the IDT72V3674. After all the offset registers are programmed from Port A,
PARALLEL LOAD FROM PORT A
IP Mode
To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master
After this reset is complete, the first four writes to FIFO1 do not store data
1,024
256
64
16
X
X
8
X
X
X
(4, 5)
(3, 5)
(1)
COMMERCIAL TEMPERATURE RANGE
X2 AND Y2 REGlSTERS
Parallel programming via Port A
Serial programming via SD
IP Mode
1,024
256
64
16
X
X
X
X
X
8
(4, 5)
(2)
(3, 5)