IDT72V3674L15PF IDT, Integrated Device Technology Inc, IDT72V3674L15PF Datasheet - Page 2

• Manufacturer Part Number: IDT72V3674L15PF
• Description: IC FIFO 16384X36 15NS 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3674L15PF

• Function: Asynchronous
• Memory Size: 576K (16K x 36)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Configuration: Dual
• Density: 576Kb
• Access Time (max): 10ns
• Word Size: 36b
• Organization: 8Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3674L15PF

PIN CONFIGURATION
DESCRIPTION
ible versions of the IDT723654/723664/723674, designed to run off a 3.3V
supply for exceptionally low-power consumption. These devices are mono-
lithic, high-speed, low-power, CMOS bidirectional synchronous (clocked)
FIFO memory which supports clock frequencies up to 100 MHz and has read
IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
The IDT72V3654/72V3664/72V3674 are pin and functionally compat-
BE/FWFT
INDEX
W/RA
CLKA
GND
GND
GND
GND
GND
ENA
A35
A34
A33
A32
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
Vcc
Vcc
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
TQFP (PK128-1, order code: PF)
TM
WITH BUS-MATCHING
TOP VIEW
2
access times as fast as 6.5ns. Two independent 2,048/4,096/8,192 x 36 dual-
port SRAM FIFOs on board each chip buffer data in opposite directions. FIFO
data on Port B can be input and output in 36-bit, 18-bit, or 9-bit formats with a
choice of Big- or Little-Endian configurations.
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
These devices are a synchronous (clocked) FIFO, meaning each port
COMMERCIAL TEMPERATURE RANGE
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
4664 drw 02
CLKB
PRS2/RT2
Vcc
B35
B34
B33
B32
RTM
GND
B31
B30
B29
B28
B27
B26
Vcc
B25
B24
BM
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
SIZE
Vcc
B15
B14
B13
B12
GND
B11
B10