IDT72V3674L15PF IDT, Integrated Device Technology Inc, IDT72V3674L15PF Datasheet - Page 13

• Manufacturer Part Number: IDT72V3674L15PF
• Description: IC FIFO 16384X36 15NS 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3674L15PF

• Function: Asynchronous
• Memory Size: 576K (16K x 36)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Configuration: Dual
• Density: 576Kb
• Access Time (max): 10ns
• Word Size: 36b
• Organization: 8Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3674L15PF

the Port B Full/Input Ready flag (FFB/IRB) is set HIGH, and both FIFOs begin
normal operation. Refer to Figure 5 for a timing diagram illustration of parallel
programming of the flag offset values.
INTERSPERSED PARITY
Table 1 for the set-up configuration of Interspersed Parity. The Interspersed
Parity function allows the user to select the location of the parity bits in the word
loaded into the parallel port (A0-An) during programming of the flag offset values.
If Interspersed Parity is selected then during parallel programming of the flag
TABLE 2 — PORT A ENABLE FUNCTION TABLE
TABLE 3 — PORT B ENABLE FUNCTION TABLE
offset values, the device will ignore data line A8. If Non-Interspersed Parity is
selected then data line A8 will become a valid bit. If Interspersed Parity is selected
serial programming of the offset values is not permitted, only parallel program-
ming can be done.
— SERIAL LOAD
with FS2 LOW, FS0/SD LOW and FS1/SEN HIGH during the LOW-to-HIGH
transition of MRS1 and MRS2. After this reset is complete, the X and Y register
values are loaded bit-wise through the FS0/SD input on each LOW-to-HIGH
transition of CLKA that the FS1/SEN input is LOW. There are 44-, 48-, or 52-
bit writes needed to complete the programming for the IDT72V3654, IDT72V3664,
or IDT72V3674, respectively. The four registers are written in the order Y1,
IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
Interspersed Parity is selected during a Master Reset of the FIFO. Refer to
To program the X1, X2, Y1, and Y2 registers serially, initiate a Master Reset
CSB
CSA
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
W/RB
W/RA
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
ENB
ENA
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
MBB
MBA
H
H
H
H
H
H
X
X
X
X
L
L
L
L
L
L
CLKB
CLKA
↑
↑
↑
↑
↑
↑
↑
↑
X
X
X
X
X
X
X
X
TM
WITH BUS-MATCHING
13
X1, Y2, and finally, X2. The first-bit write stores the most significant bit of the Y1
register and the last-bit write stores the least significant bit of the X2 register. Each
register value can be programmed from 1 to 2,044 (IDT72V3654), 1 to 4,092
(IDT72V3664), or 1 to 8,188 (IDT72V3674).
A Full/Input Ready (FFA/IRA) flag remains LOW until all register bits are written.
FFA/IRA is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit
is loaded to allow normal FIFO1 operation. The Port B Full/Input Ready (FFB/
IRB) flag also remains LOW throughout the serial programming process, until
all register bits are written. FFB/IRB is set HIGH by the LOW-to-HIGH transition
Data B (B0-B35) I/O
of CLKB after the last bit is loaded to allow normal FIFO2 operation. See Figure 6
for Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset
Values (IDT Standard and FWFT Modes) timing diagram.
FIFO WRITE/READ OPERATION
(CSA) and Port A Write/Read select (W/RA). The A0-A35 lines are in the High-
impedance state when either CSA or W/RA is HIGH. The A0-A35 lines are
active outputs when both CSA and W/RA are LOW.
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
LOW, and FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs
by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW,
Data A (A0-A35) I/O
High-Impedance
High-Impedance
When the option to program the offset registers serially is chosen, the Port
The state of the Port A data (A0-A35) lines is controlled by Port A Chip Select
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
COMMERCIAL TEMPERATURE RANGE
Mail1 read (set MBF1 HIGH)
Mail2 read (set MBF2 HIGH)
Port Function
Port Function
FIFO1 write
FIFO2 write
FIFO2 read
FIFO1 read
Mail1 write
Mail2 write
None
None
None
None
None
None
None
None