IDT72V3674L15PF IDT, Integrated Device Technology Inc, IDT72V3674L15PF Datasheet - Page 26

• Manufacturer Part Number: IDT72V3674L15PF
• Description: IC FIFO 16384X36 15NS 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3674L15PF

• Function: Asynchronous
• Memory Size: 576K (16K x 36)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Configuration: Dual
• Density: 576Kb
• Access Time (max): 10ns
• Word Size: 36b
• Organization: 8Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3674L15PF

NOTES:
1. t
2. If Port B size is word or byte, t
A0-A35
B0-B35
IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
W/RA
If the time between the CLKB edge and the rising CLKA edge is less than t
cycle later than shown.
W/RB
CLKA
CLKB
SKEW1
MBA
MBB
ORA
CSA
CSB
ENA
ENB
IRB
is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
FIFO2 Empty
LOW
LOW
HIGH
LOW
LOW
LOW
Figure 17. ORA Flag Timing and First Data Word Fall through when FIFO2 is Empty (FWFT Mode
t
t
ENS2
ENS2
t
DS
SKEW1
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
W1
Old Data in FIFO2 Output Register
t
SKEW1
t
t
t
ENH
DH
ENH
(1)
t
CLKH
1
t
CLK
SKEW1
t
TM
CLKL
WITH BUS-MATCHING
, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
t
CLKH
26
2
t
CLK
t
REF
3
t
A
t
CLKL
t
ENS2
COMMERCIAL TEMPERATURE RANGE
t
REF
t
ENH
W1
)
4664 drw19