IDT72V3674L15PF IDT, Integrated Device Technology Inc, IDT72V3674L15PF Datasheet

IC FIFO 16384X36 15NS 128QFP

IDT72V3674L15PF

Manufacturer Part Number
IDT72V3674L15PF
Description
IC FIFO 16384X36 15NS 128QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet

Specifications of IDT72V3674L15PF

Function
Asynchronous
Memory Size
576K (16K x 36)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Configuration
Dual
Density
576Kb
Access Time (max)
10ns
Word Size
36b
Organization
8Kx36x2
Sync/async
Synchronous
Expandable
No
Bus Direction
Bi-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Supply Current
400mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V3674L15PF
FEATURES
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
FUNCTIONAL BLOCK DIAGRAM
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
© 2009
EFA/ORA
FS1/SEN
Memory storage capacity:
Clock frequencies up to 100 MHz (6.5ns access time)
Two independent clocked FIFOs buffering data in opposite
directions
Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRB flag functions)
Programmable Almost-Empty and Almost-Full flags; each has five
default offsets (8, 16, 64, 256 and 1,024 )
Serial or parallel programming of partial flags
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
FFA/IRA
RTM
RT1
RT2
FS0/SD
MRS1
A
MBF2
PRS1
CLKA
W/RA
0
MBA
CSA
ENA
AFA
AEA
IDT72V3654
IDT72V3664
IDT72V3674
FS2
-A
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
35
FIFO1 and
FIFO2
Retransmit
Logic
Control
Port-A
FIFO1,
Mail1
Reset
Logic
Logic
– 2,048 x 36 x 2
– 4,096 x 36 x 2
– 8,192 x 36 x 2
36
36
13
3.3 VOLT CMOS SyncBiFIFO
2,048 x 36 x 2
4,096 x 36 x 2
8,192 x 36 x 2
FIFO1
FIFO2
Programmable Flag
Offset Registers
36
Pointer
Pointer
Read
Write
36
Status Flag
Status Flag
RAM ARRAY
2,048 x 36
4,096 x 36
8,192 x 36
RAM ARRAY
2,048 x 36
4,096 x 36
8,192 x 36
Register
Register
Mail 1
Mail 2
Logic
Logic
Pointer
Pointer
1
Timing
Read
Write
Mode
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
36
Big- or Little-Endian format for word and byte bus sizes
Retransmit Capability
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
Auto power down minimizes power dissipation
Available in space saving 128-pin Thin Quad Flatpack (TQFP)
Pin and functionally compatible version of the 5V operating
IDT723654/723664/723674
Pin compatible to the lower density parts, IDT72V3624/72V3634/
72V3644
Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available
Green parts available, see ordering information
36
TM
WITH BUS-MATCHING
FEBRUARY 2009
36
36
Control
Port-B
FIFO2,
Mail2
Reset
Logic
Logic
IDT72V3654
IDT72V3664
IDT72V3674
4664 drw01
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
MBF1
EFB/ORB
AEB
FWFT
B
FFB/IRB
AFB
MRS2
PRS2
DSC-4664/6
0
-B
35

Related parts for IDT72V3674L15PF

IDT72V3674L15PF Summary of contents

Page 1

FEATURES • • • • • Memory storage capacity: IDT72V3654 – 2,048 IDT72V3664 – 4,096 IDT72V3674 – 8,192 • • • • • Clock frequencies up to 100 ...

Page 2

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 DESCRIPTION The IDT72V3654/72V3664/72V3674 are pin and functionally compat- ible versions of the IDT723654/723664/723674, designed to run off a 3.3V supply ...

Page 3

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged ...

Page 4

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 PIN DESCRIPTIONS Symbol Name I/O A0-A35 Port A Data I/O AEA Port A Almost- O Empty Flag AEB Port B ...

Page 5

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O FS0/SD Flag Offset Select 0/ I Serial Data FS1/SEN Flag Offset Select 1/ I ...

Page 6

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O W/RA Port-A Write/ I Read Select W/RB Port-B Write/ I Read Select TM WITH ...

Page 7

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted) Symbol V Supply Voltage Range CC (2) V Input ...

Page 8

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The I current for the graph in Figure 1 was taken while simultaneously ...

Page 9

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (For 10ns speed grade only: Vcc = 3.3V ...

Page 10

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C (For 10ns speed grade only: Vcc = ...

Page 11

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 SIGNAL DESCRIPTION MASTER RESET (MRS1, MRS2) After power up, a Master Reset operation must be performed by providing a LOW ...

Page 12

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW on the BE/ FWFT input during the next LOW-to-HIGH ...

Page 13

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 the Port B Full/Input Ready flag (FFB/IRB) is set HIGH, and both FIFOs begin normal operation. Refer to Figure 5 ...

Page 14

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 TABLE 4 — FIFO1 FLAG OPERATION (IDT Standard and FWFT modes) Number of Words in FIFO Memory (3) IDT72V3654 IDT72V3664 ...

Page 15

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 SYNCHRONIZED FIFO FLAGS Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done ...

Page 16

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 LOW-to-HIGH transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to [2,048/4,096/8,192-(Y+1)]. ...

Page 17

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 BYTE ORDER ON PORT A: B35 ⎯ B27 BYTE ORDER ON PORT SIZE ...

Page 18

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 CLKA CLKB t RSTS MRS1 BE/FWFT FS2, FS1,FS0 FFA/IRA EFB/ORB t RSF AEB t RSF AFA t RSF MBF1 LOW ...

Page 19

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 CLKA 1 4 MRS1, MRS2 t FSS t FSH FS2 t t FSS FSH FS1,FS0 0,0 FFA/IRA ENA A0-A35 CLKB ...

Page 20

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 CLK t CLKH t CLKL CLKA FFA/IRA HIGH t ENS1 CSA t ENS1 W/RA t ENS2 MBA t ENS2 ...

Page 21

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 CLKB FFB/IRB HIGH CSB W/RB MBB ENB B0-B17 DATA SIZE TABLE FOR WORD WRITES TO FIFO2 (1) SIZE MODE WRITE ...

Page 22

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 CLK t CLKH CLKB EFB/ORB HIGH CSB W/RB MBB ENB t EN B0-B35 (Standard Mode B0-B35 ...

Page 23

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 CLKB EFB/ORB HIGH CSB W/RB MBB t ENS2 ENB t MDV t EN B0-B8 (Standard Mode) t MDV OR t ...

Page 24

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 CLKA CSA LOW WRA HIGH t t ENS2 ENH MBA t t ENS2 ENH ENA IRA HIGH ...

Page 25

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 CLKA CSA LOW HIGH WRA t t ENS2 ENH MBA t t ENH ENS2 ENA FFA HIGH ...

Page 26

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 CLKB CSB LOW W/RB LOW t t ENS2 ENH MBB t t ENH ENS2 ENB IRB HIGH ...

Page 27

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 CLKB CSB LOW W/RB LOW t t ENS2 ENH MBB t t ENS2 ENH ENB FFB HIGH ...

Page 28

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB ORB HIGH B0-B35 Previous ...

Page 29

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA LOW MBA t ENS2 ENA ORA HIGH A0-A35 Previous ...

Page 30

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA LOW MBA t ENS2 ENA EFA HIGH A0-A35 Previous ...

Page 31

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 CLKA t t ENS2 ENH ENA t SKEW2 CLKB AEB X1 Words in FIFO1 ENB NOTES: is the minimum time ...

Page 32

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 CLKB t ENS2 ENB AFB [D-(Y2+1)] Words in FIFO2 CLKA ENA NOTES: is the minimum time between a rising CLKB ...

Page 33

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 CLKB CSB W/RB MBB ENB B0-B35 CLKA MBF2 CSA W/RA MBA ENA t EN A0-A35 FIFO2 Output Register NOTE: 1. ...

Page 34

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 CLKA 1 2 CLKB 2 1 ENB t RSTS RT1 t RTMS RTM EFB B0-Bn NOTES: 1. CSB = LOW ...

Page 35

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 CLKA 1 2 CLKB 1 LOW ENB t RSTS RT1 t RTMS RTM ORB B0-Bn NOTES: 1. CSB = LOW ...

Page 36

IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO 2,048 4,096 and 8,192 PARAMETER MEASUREMENT INFORMATION From Output Under Test Timing 1.5 V Input Data, 1.5 V Enable Input ...

Page 37

ORDERING INFORMATION XXXXXX Device Type Power Speed Package NOTES: 1. Industrial temperature range is available by special order. 2. Green parts available. For specific speeds and packages contact your sales office. DATASHEET DOCUMENT HISTORY 06/13/2000 pgs. 1-3, ...

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