MT28F004B3VG-8BET Micron, MT28F004B3VG-8BET Datasheet - Page 11

• Manufacturer Part Number: MT28F004B3VG-8BET
• Description: 512K x 8 3V only, dula supply, smart 3 boot block flash memory
• Manufacturer: Micron

contents on DQ0–DQ7 without prior command. While
the status register contents are read, the outputs are not
updated if there is a change in the ISM status unless OE#
or CE# is toggled. If the device is not in the write, erase,
erase suspend or status register read mode, READ STA-
TUS REGISTER (70h) can be issued to view the status
register contents.
ISM and erase suspend status bits are reset by the ISM.
The erase, write and V
4Mb Smart 3 Boot Block Flash Memory
F45_3.p65 – Rev. 3, Pub. 12/01
STATUS
SR0-2
BIT #
SR7
SR6
SR5
SR4
SR3
All of the defined bits are set by the ISM, but only the
STATUS REGISTER BIT
ISM STATUS (ISMS)
1 = Ready
0 = Busy
ERASE SUSPEND STATUS (ESS)
1 = ERASE suspended
0 = ERASE in progress/completed
ERASE STATUS (ES)
1 = BLOCK ERASE error
0 = Successful BLOCK ERASE
WRITE STATUS (WS)
1 = WORD/BYTE WRITE error
0 = Successful WORD/BYTE WRITE by a CLEAR STATUS REGISTER command or after a RESET.
V
1 = No V
0 = V
RESERVED
PP
STATUS (V
PP
present
ISMS
PP
PP
7
voltage detected
status bits must be cleared using
PP
S)
ESS
6
Status Register Bit Definitions
The ISMS bit displays the active status of the state machine during
WRITE or BLOCK ERASE operations. The controlling logic polls this
and sets this and the ISMS bit to “1.” The ESS bit remains “1”
ES is set to “1” after the maximum number of ERASE cycles is
executed by the ISM without a successful verify. ES is only cleared
by a CLEAR STATUS REGISTER command or after a RESET.
WS is set to “1” after the maximum number of WRITE cycles is
executed by the ISM without a successful verify. WS is only cleared
continuously, nor does it indicate a valid V
DESCRIPTION
bit to determine when the erase and write status bits are valid.
Issuing an ERASE SUSPEND places the ISM in the suspend mode
until an ERASE RESUME is issued.
V
sampled for 3.3V or 5V after WRITE or ERASE CONFIRM is given.
V
Reserved for future use.
PP
PP
ES
SMART 3 BOOT BLOCK FLASH MEMORY
5
S detects the presence of a V
S must be cleared by CLEAR STATUS REGISTER or by a RESET.
Table 2
11
CLEAR STATUS REGISTER. If the V
set, the CEL does not allow further WRITE or ERASE
operations until the status register is cleared. This en-
ables the user to choose when to poll and clear the status
register. For example, the host system may perform mul-
tiple BYTE WRITE operations before checking the status
register instead of checking after each individual WRITE.
Asserting the RP# signal or powering down the device
also clears the status register.
WS
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
V
PP
3
PP
S
voltage. It does not monitor V
PP
2–0
voltage. The V
R
PP
status bit (SR3) is
©2001, Micron Technology, Inc.
4Mb
PP
pin is
PP