MT9196AS Zarlink Semiconductor, Inc., MT9196AS Datasheet
MT9196AS
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MT9196AS Summary of contents
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... XSTL2 WD PWRST Integrated Digital Phone Circuit (IDPC) MT9196AE MT9196AP MT9196AS Description The MT9196 Integrated Digital Phone Circuit (IDPC) is designed for use in digital phone products. The device incorporates a built-in Filter/Codec, digital gain pads, DTMF generator and tone ringer. Complete telephony interfaces are provided for connecting transducers ...
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MT9196 PWRST VSSD SCLK 10 20 DATA1 11 19 DATA2 PIN PLCC Pin ...
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Pin Description (continued) Pin # Name 16 STB/F0i Data Strobe/Frame Pulse (Input). For SSI mode this input determines the 8 bit timeslot used by the device for both transmit and receive data. This active high signal has a repetition rate ...
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MT9196 Overview The functional block diagram of Figure 1 depicts the main operations performed by the MT9196 IDPC. Each of these functional blocks will be described individually in the sections to follow. This overview will describe some of the end-user ...
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On PWRST (pin 5) the Filter/CODEC defaults such that the side-tone path, dial tone filter and 400 Hz transmit filter are off, all programmable gains are set to 0dB and CCITT -Law is selected. Further, the Filter/CODEC is powered down ...
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MT9196 The receive filter is designed to meet CCITT G.714 specifications. The nominal gain for this filter path (gain control = 0dB). Gain control allows the output signal to be attenuated dB. Filter response ...
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Low and high tones are enabled individually via the LoEn and HiEN control bits (DTMF/Ringer Control Register, address 18h). This not only provides control over dual tone generation but also allows single tone generation using either of the enable bits ...
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MT9196 limited to -24 dB regardless of the mathematical result of this operation. The path without loss reverts to the gain value programmed into the Digital Gain Register. The magnitude of the switched loss defaults power ...
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This mode can be used to implement a loudspeaking function where the receive audio is routed to the SPKR pins and transmit audio is sourced from the MIC+ pin. In this mode there is no algorithmic cancellation of echo so ...
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MT9196 IDPC. During a valid read transfer from IDPC data simultaneously clocked out by the micro is ignored by IDPC. All data transfers through the microport are two-byte transfers requiring the transmission of a Command/ Address byte followed by the ...
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F0i DSTi, CHANNEL 0 CHANNEL 1 D-channel C-channel DSTo LSB first MSB first for C, B1- & B2- for D- Channel between the IDPC and the microcontroller. At the end of the two-byte transfer CS is brought high again to ...
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MT9196 beginning with Channel 0 after the frame pulse, as shown in Figure 7 (ST-BUS channel assignments). The first two (D & C) Channels are enabled for use by the DEN and CEN bits respectively, (FDI Control Register, address 10h). ...
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IRQ FP n-3 n-2 DSTo/ DSTi Di-bit Group I II Receive D-Channel No preset value * note that frame n+4 is equivalent to frame n of the next cycle. FP C4i C2 Din D0 IRQ 8 ...
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MT9196 bit first, on DSTo. On power-up reset (PWRST) or software reset (RST, address 0Fh) all C-Channel bits default to logic high. Receive C-Channel data (DSTi) is always routed to the read register regardless of this control bit's logic state. ...
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Asynch/ Bit Clock CSL1 CSL0 Rate (kHz) Synch 128 256 512 1536 2048 4096 Table 3 For synchronous operation data is sampled, ...
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MT9196 Sidetone A voice sidetone path provides proportional transmit signal summing into the receive handset transducer driver. Details are provided in the Filter/CODEC section. Watchdog To maintain program integrity an on-chip watchdog timer is provided for connection microcontroller reset pin. ...
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RxFG RxFG 2 0B Gain3 Gain2 Gain1 0C ---------------------------------------RESERVED---------------------------------- 0D ---------------------------------------RESERVED---------------------------------- 0E PD Tfhp DialEn 0F RST - ST-BUS/ CEN SSI ...
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MT9196 Register Summary Filter Codec Control Register 1 - RxFG RxFG Receive Gain RxFG 2 Setting (dB (default RxFG = ...
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Control Register 1 PD Tfhp DialEN When high, the crystal oscillator and FDI blocks are powered down. When low, the oscillator and FDI circuits are active. Tfhp When High, an additional highpass function (passband beginning at ...
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MT9196 FDI Control Register ST-BUS/ - CEN SSI ST-BUS/SSI When high, the FDI port operates in ST-BUS mode. When low, the FDI operates in SSI mode. CEN When high, data written into the C-Channel register (address 14h) ...
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Transmit Path Control Register - - - Control bits are used to configure the transmit path and select the transmit source. Note that for SSI mode all selections where are not ...
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MT9196 C-Channel Register Micro-port access to the ST-BUS C-Channel information D-Channel Register Loopback Register - - Loop2 Loop1 When high, the selected B-channel in ST-BUS ...
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DTMF/Tone Ringer Control Register DTMF LoEN HiEN HiEN, LoEN When high, the programmed tone, for the respective high or low group, is generated. When low, tone generation is disabled for the respective low or high ...
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MT9196 High Tone Coefficient Register The frequency of the high group tone is programmed by writing an 8-bit hexadecimal coefficient at this address according to the following equation: Where the hexadecimal COEFF is converted ...
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Applications Typical External Gain for Handset AV Typical External Gain for MIC AV 0 INTEL SCLK 9 MCS- DATA1 MOTOROLA SPI 11 DATA2 ...
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MT9196 Typical External Gain for Handset AV Typical External Gain for MIC AV 0 INTEL 9 SCLK MCS- DATA1 MOTOROLA SPI 11 DATA2 ...
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Programming Examples Some examples of the programming steps required to set-up various telephony functions are given. Note Initialization Description choose ST-BUS vs SSI (ie ST-BUS with C&D channels enabled) or (ie SSI at 256kHz BCL) power up oscillator and FDI ...
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MT9196 Generate tone ringer Description Program Initialization steps above except A-Law vs -Law choices are not required. set speaker gain (ie -12dB) write low tone coefficient write high tone coefficient select ringer as source for loudspeaker start tone ringer (warble ...
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Absolute Maximum Ratings Parameter 1 Supply Voltage 2 Voltage on any I/O pin 3 Current on any I/O pin (transducers excluded) 4 Storage Temperature 5 Power Dissipation (package) Recommended Operating Conditions Characteristics 1 Supply Voltage 2 TTL Input Voltage (high)* ...
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MT9196 DC Electrical Characteristics Characteristics 1 Input HIGH Voltage TTL inputs 2 Input LOW Voltage TTL inputs 3 Input HIGH Voltage CMOS inputs 4 Input LOW Voltage CMOS inputs 5 VBias Voltage Output 6 Input Leakage Current 7 Positive Going ...
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AC Characteristics for A/D (Transmit) Path A-Law, at the CODEC. (V =1.0 volts and V Ref Characteristics 1 Analog input equivalent to overload decision 2 Absolute half-channel gain M to PCM MIC + to PCM AUXin to PCM Tolerance ...
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MT9196 † AC Characteristics for D/A (Receive) Path (V =1.0 volts and V =2.5 volts.) Ref Bias Characteristics 1 Analog output at the CODEC full scale 2 Absolute half-channel gain PCM to HSPKR PCM to SPKR PCM to AUXout Tolerance ...
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AC Characteristics for Auxiliary Analog LoopbackPath Characteristics 1 Absolute gain for analog loopback from Auxiliary port. AUXin to HSPKR AUXin to SPKR AUXin to AUXout † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ...
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MT9196 † Electrical Characteristics for Analog Inputs Characteristics 1 Input voltage without overloading CODEC at MIC+ at AUXin across M+/M- 2 Input impedance † Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are ...
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AC Electrical Characteristics Characteristics 1 BCL Clock Period 2 BCL Pulse Width High 3 BCL Pulse Width Low 4 BCL Rise/Fall Time 5 Strobe Pulse Width 6 Strobe setup time before BCL falling 7 Strobe hold time after BCL falling ...
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MT9196 AC Electrical Characteristics Characteristics 1 Bit Cell Period 2 Frame Jitter 3 Bit 1 Dout Delay from STB going high 4 Bit 2 Dout Delay from STB going high 5 Bit n Dout Delay from STB going high 6 ...
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AC Electrical Characteristics Characteristics 1 Input data setup 2 Input data hold 3 Output data delay 4 Serial clock period 5 SCLK pulse width high 6 SCLK pulse width low 7 CS setup-Intel 8 CS setup-Motorola 9 CS hold 10 ...
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MT9196 Notes: 7-172 ...
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Package Outlines Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 8-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.115 (2.92) ...
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Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 22-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.125 (3.18) 0.195 ...
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Package Outlines Dim D General- (lead coplanarity) A Notes Not ...
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16-Pin DIM Min Max Min A 0.093 0.104 0.093 (2.35) (2.65) (2.35) A 0.004 0.012 0.004 1 (0.10) (0.30) (0.10) B 0.013 0.020 0.013 (0.33) (0.51) (0.33) C 0.009 0.013 0.009 (0.231) (0.318) (0.231) D 0.398 0.413 ...
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