MT9196AS Zarlink Semiconductor, Inc., MT9196AS Datasheet - Page 10

• Manufacturer Part Number: MT9196AS
• Description: Integrated Digital Phone Circuit (IDPC)
• Manufacturer: Zarlink Semiconductor, Inc.

MT9196
IDPC. During a valid read transfer from IDPC data
simultaneously clocked out by the micro is ignored
by IDPC.
All data transfers through the microport are two-byte
transfers requiring the transmission of a Command/
Address byte followed by the data byte written or
read from the addressed register. CS must remain
asserted for the duration of this two-byte transfer. As
7-144
DATA 1
RECEIVE
DATA 1
TRANSMIT
SCLK
CS
DATA 2
RECEIVE
DATA 1
TRANSMIT
SCLK
CS
subsequent byte is always data until terminated via CS returning high.
subsequent byte is always data until terminated via CS returning high.
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
Delays due to internal processor timing which are transparent to IDPC.
The IDPC:- latches received data on the rising edge of SCLK.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
Delays due to internal processor timing which are transparent to IDPC.
The IDPC:- latches received data on the rising edge of SCLK.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
D
D
7
0
- outputs transmit data on the falling edge of SCLK.
- outputs transmit data on the falling edge of SCLK.
D
D
Figure 6 - Serial Port Relative Timing for Motorola Mode 00/National Microwire
COMMAND/ADDRESS
6
COMMAND/ADDRESS
1
D
D
5
2
D
D
4
3
D
D
3
4
Figure 5 - Serial Port Relative Timing for Intel Mode 0
D
D
2
5
D
D
1
6
D
D
0
7
1 bit - Read/Write
5 bits - Addressing Data
2 bits - Unused
1 bit - Read/Write
5 bits - Addressing Data
2 bits - Unused
D
D
D
D
0
7
7
0
D
D
D
D
1
6
6
1
DATA INPUT/OUTPUT
DATA INPUT/OUTPUT
D
D
D
D
2
5
5
2
D
D
D
D
4
3
3
4
D
D
D
shown in Figures 5 and 6 the falling edge of CS
indicates to the IDPC that a microport transfer is
about to begin. The first 8 clock cycles of SCLK after
the falling edge of CS are always used to receive the
Command/Address byte from the microcontroller.
The Command/Address byte contains information
detailing whether the second byte transfer will be a
read or a write operation and at what address. The
next 8 clock cycles are used to transfer the data byte
D
3
4
4
3
D
D
D
D
2
5
5
2
D
D
D
D
1
6
6
1
D
R/W
X
7
D
D
D
D
D
7
0
7
7
0
X
X
D
D
D
D
7
0
A
7
0
A
4
4
D
D
D
D
6
1
6
1
COMMAND/ADDRESS:
COMMAND/ADDRESS:
A
D
D
D
D
A
3
5
2
2
5
3
D
D
D
D
3
4
3
A
4
A
2
D
D
2
D
D
4
3
4
3
D
D
A
D
D
A
1
5
2
5
2
1
D
D
D
D
6
1
6
1
A
A
0
D
D
D
D
0
7
0
0
7
R/W
D
D
X
0
0