AD9642BCPZRL7-250 Analog Devices, Inc., AD9642BCPZRL7-250 Datasheet - Page 21

• Manufacturer Part Number: AD9642BCPZRL7-250
• Description: 14-bit, 170 Msps/210 Msps/250 Msps, 1.8 V Analog-to-digital Converter Adc
• Manufacturer: Analog Devices, Inc.

Timing
The
10 input sample clock cycles. Data outputs are available one
propagation delay (t
Minimize the length of the output data lines as well as the loads
placed on these lines to reduce transients within the AD9642.
These transients may degrade converter dynamic performance.
Table 10. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
AD9642
provides latched data with a pipeline delay of
VIN+ − VIN−,
Input Span = 1.75 V p-p (V)
<–0.875
−0.875
0
+0.875
>+0.875
PD
) after the rising edge of the clock signal.
Offset Binary Output Mode
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
Rev. 0 | Page 21 of 28
The lowest typical conversion rate of the
At clock rates below 40 MSPS, dynamic performance may
degrade.
Data Clock Output (DCO)
The
for capturing the data in an external register. Figure 2 shows a
timing diagram of the
AD9642
also provides the data clock output (DCO) intended
AD9642
Twos Complement Mode (Default)
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
output modes.
AD9642
is 40 MSPS.
AD9642