AD9642BCPZRL7-250 Analog Devices, Inc., AD9642BCPZRL7-250 Datasheet - Page 22

• Manufacturer Part Number: AD9642BCPZRL7-250
• Description: 14-bit, 170 Msps/210 Msps/250 Msps, 1.8 V Analog-to-digital Converter Adc
• Manufacturer: Analog Devices, Inc.

AD9642
SERIAL PORT INTERFACE (SPI)
The
configure the converter for specific functions or operations
through a structured register space provided inside the ADC.
The SPI offers added flexibility and customization, depending
on the application. Addresses are accessed via the serial port
and can be written to or read from via the port. Memory is
organized into bytes that can be further divided into fields.
These fields are documented in the Memory Map section. For
detailed operational information, see the
Note, Interfacing to High Speed ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK pin, the SDIO pin,
and the CSB pin (see Table 11). The SCLK (serial clock) pin is
used to synchronize the read and write data presented from and
to the ADC. The SDIO (serial data input/output) pin is a dual-
purpose pin that allows data to be sent and read from the internal
ADC memory map registers. The CSB (chip select bar) pin is an
active low control that enables or disables the read and write cycles.
Table 11. Serial Port Interface Pins
Pin
SCLK
SDIO
CSB
The falling edge of CSB, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the
serial timing and its definitions can be found in Figure 58 and
Table 5.
Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. The CSB can stall high between bytes
to allow for additional external timing. When CSB is tied high,
SPI functions are placed in a high impedance mode. This mode
turns on any SPI pin secondary functions.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits.
AD9642
Function
Serial clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
Serial data input/output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Chip select bar. An active low control that gates the read
and write cycles.
serial port interface (SPI) allows the user to
AN-877 Application
Rev. 0 | Page 22 of 28
All data is composed of 8-bit words. The first bit of each
individual byte of serial data indicates whether a read or write
command is issued. This allows the serial data input/output
(SDIO) pin to change direction from an input to an output.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read the
contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
Data can be sent in MSB first mode or in LSB first mode. MSB first
mode is the default on power-up and can be changed via the SPI
port configuration register. For more information about this and
other features, see the
High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 11 comprise the physical interface
between the user programming device and the serial port of the
AD9642. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the
controller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the
tioning at the converter inputs during critical sampling periods.
AD9642
AN-877 Application
to prevent these signals from transi-
AN-812 Application
Note, Interfacing to
Note, Micro-