upd72872 Renesas Electronics Corporation., upd72872 Datasheet
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IEEE1394 1-CHIP OHCI HOST CONTROLLER The µ PD72872 is the LSI which integrated OHCI-Link and PHY function into a single chip. The µ PD72872 complies with the P1394a draft 2.0 specifications and the OpenHCI IEEE1394 1.0, and works up to ...
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Firewarden™ ROADMAP IEEE1394-1995 Core Development Link Core 2 Firewarden Series 1 Chip OHCI Link OHCI+PHY µ PD72862 µ PD72872 1 Chip OHCI+PHY OHCI Link µ PD72870A µ PD72861 1 Chip OHCI+PHY OHCI Link µ PD72870 µ PD72860 Data Sheet S14793EJ1V0DS ...
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BLOCK DIAGRAMS Top Block Diagram Serial ROM Interface PCI Bus/ Cardbus PHY PHY Analog Link PHY Digital Data Sheet S14793EJ1V0DS PHY Signal 3 ...
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PHY Block Diagram PHY Control Signal Link PHY/Link Interface Interface I/O Cable Power Status Remark Cable Port: 4 Cable Port1 Arbitration Cable and Control Port2 State Machine Logic Voltage and Receive Data Current Decoder and Generator Retimer Crystal Oscillator PLL ...
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Link Block Diagram PCI Controller Interface (Master, Parity Check & Generator) Byte Buf Swap OPCI Internal Bus PCIS_CNT OPCIBUS_ARB ATDMA : Asynchronous Transmit DMA ATF : Asynchronous Transmit FIFO CIS : CIS Register CSR : Control and Status Registers IOREG ...
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PIN CONFIGURATION (TOP VIEW) • 120-pin plastic TQFP (Fine pitch) (14 x 14) µ µ µ µ PD72872GC-9EV L_V 1 DD CLKRUN 2 PME 3 INTA 4 PRST 5 PCLK 6 GNT 7 REQ 8 AD31 9 AD30 10 DGND ...
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PIN NAME AD0-AD31 : PCI Multiplexed Address and Data AGND : Analog GND CARD_ON : PCI/Card Select CBE0-CBE3 : Command/Byte Enables CLKRUN : PCICLK Running CPS : Cable Power Status Input DEVSEL : Device Select DGND : Digital GND FRAME ...
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PIN FUNCTIONS................................................................................................................................... 10 1.1 PCI/Cardbus Interface Signals: (52 pins) .................................................................................... 10 1.2 PHY Signals: (16 pins) .................................................................................................................. 12 1.3 PHY Control Signals: (4 pins)....................................................................................................... 12 1.4 PCI/Cardbus Select Signal: (1 pin)............................................................................................... 12 1.5 Serial ROM Interface Signals: (3 pins)......................................................................................... ...
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PHY FUNCTION.................................................................................................................................... 30 4.1 Cable Interface............................................................................................................................... 30 4.1.1 Connections ......................................................................................................................................... 30 4.1.2 Cable Interface Circuit.......................................................................................................................... 31 4.1.3 CPS ...................................................................................................................................................... 31 4.1.4 Unused Ports........................................................................................................................................ 31 4.2 PLL and Crystal Oscillation Circuit ............................................................................................. 31 4.2.1 Crystal Oscillation Circuit ..................................................................................................................... 31 4.2.2 ...
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PIN FUNCTIONS 1.1 PCI/Cardbus Interface Signals: (52 pins) Name I/O Pin No. PAR I/O 44 AD0-AD31 I/O 9, 10, 12, 13, 15- 18, 23, 24, 26-29, 32, 33, 47-50, 52, 53, 55, 56, 58, 59, 62, 63, 65-68 CBE0-CBE3 ...
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Name I/O Pin No. CLKRUN I/O 2 PCI/Cardbus INTA O 4 PCI/Cardbus PERR I/O 41 PCI/Cardbus SERR O 42 PCI/Cardbus PRST I 5 PCLK I 6 Remark *: If the Link pin is pulled up, it should be connected to ...
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PHY Signals: (16 pins) Name I/O Pin No. TpA0p I/O 105 TpA0n I/O 104 TpB0p I/O 103 TpB0n I/O 102 TpA1p I/O 101 TpA1n I/O 100 TpB1p I/O 99 TpB1n I/O 98 PORTDIS I 78 CPS I 93 TpBias0 ...
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Serial ROM Interface Signals: (3 pins) Name I/O Pin No. GROM_SDA I/O 116 GROM_SCL O 117 GROM_EN I 118 1.6 IC: (7 pins) Name I/O Pin No. IC(H) I 74, 75 IC(L) I 76, 77, 114, 115 IC(N) - ...
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PHY REGISTERS 2.1 Complete Structure for PHY Registers Figure 2-1. Complete Structure of PHY Registers 0 1 0000 0001 RHB IBR 0010 Extended (7) 0011 Max_speed 0100 Link_active Contender 0101 Resume_int ISBR 0110 0111 Page_select 1000 1001 1010 1011 ...
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Field Size R/W Reset value Extended 3 R 111 Total_ports 4 R 0010 Max_speed 3 R 010 Delay 4 R 0010 Link_active 1 R/W 1 Contender 1 R/W 0 Jitter 3 R 010 Pwr_class 3 R/W See Description Resume_int 1 ...
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Field Size R/W Reset value Loop 1 R/W Pwr_fail 1 R/W Timeout 1 R/W Port_event 1 R/W Enab_accel 1 R/W Enab_multi 1 R/W Page_select 3 R/W 000 Port_select 4 R/W 0000 Reserved - R 000… 16 Table 2-1. Bit Field ...
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Port Status Page (Page 000 1000 AStat 1001 Negotiated_speed 1010 1011 1100 1101 1110 1111 Field Size R/W Reset value AStat BStat Child 1 R Connected 1 R Bias 1 R ...
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Vendor ID Page (Page 001 1000 1001 1010 1011 1100 1101 1110 1111 Field Size R/W Reset value Compliance_level 8 R 00000001 Vendor_ID 24 R 00004CH Product_ID 24 R Reserved - R 000… 18 Figure 2-3. Vendor ...
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CONFIGURATION REGISTERS 3.1 PCI Bus Mode Configuration Register (CARD_ON = Low Device ID Status BIST Subsystem ID Max_Lat Power Management Capabilities Data # # # # # # # # # # # # 16 15 ...
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Offset_00 Vendor ID Register This register identifies the manufacturer of the µ PD72872. The ID is assigned by the PCI_SIG committee. Bits R/W 15-0 R Constant value of 1033H. 3.1.2 Offset_02 Device ID Register This register identifies the type ...
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Offset_06 Status Register This register tracks the status information of PCI-bus related events which are relevant to the µ PD72872. “Read” and “Write” are handled somewhat differently. Bits R/W 3-0 R Reserved Constant value of 0000 New ...
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Offset_08 Revision ID Register This register specifies a revision number assigned by NEC Corporation for the µ PD72872. Bits R/W 7-0 R Default value of 01H. It specifies the silicon revision. It will be incremented for subsequent silicon revisions. ...
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Offset_10 Base Address 0 Register This register specifies the base memory address for accessing all the “Operation registers” (i.e. control, configuration, and status registers) of the µ PD72872, while the BIOS is expected to set this value during power-up ...
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Offset_3C Interrupt Line Register This register provides the interrupt line routing information specific to the µ PD72872, the NEC’s implementation of the 1394 OpenHCI specification. Bits R/W 7-0 R/W Default value of 00H. It specifies which input of the ...
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Offset_60 Cap_ID & Next_Item_Ptr Register The Cap_ID signals that this item in the Linked List is the registers defined for PCI Power Management, while the Next_Item_Ptr describes the location of the next item in the µPD72872’s Capability List. Bits ...
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Offset_64 Power Management Control/Status Register This is a 16-bit read-only register that provides control status information of the µ PD72872. Bits R/W 1,0 R/W PowerState Default value is undefined. This field is used both to determine the current power ...
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CardBus Mode Configuration Register (CARD_ON = High Device ID Status BIST Subsystem ID Max_Lat Power Management Capabilities Data # # # # # # # # # # # # Note Different from PCI Bus Mode ...
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Offset_14/18 Base_Address_1/2 Register (Cardbus Status Registers) Bits R/W 7-0 R Constant value of 00. 31-8 R/W - (1) Function Event Register (FER) ( Base Address Bits R Write Protect (No Use). ...
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Function Reset Status Register (FRSR) ( Base Address Bits R Write Protect (No Use). Read only as ‘0’ Ready Status (No Use). Read only as ‘0’ Battery ...
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PHY FUNCTION 4.1 Cable Interface 4.1.1 Connections Connection Detection Current Connection Detection Comparator + - Driver Receiver + - Arbitration Comparators + - + - ...
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Cable Interface Circuit Each port is configured with two twisted-pairs of TpA and TpB. TpA and TpB are used to monitor the state of the Transmit/Receive line, control signals, data and cables. During transmission to the IEEE1394 bus, the ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Power supply voltage Input voltage Output voltage Operating ambient temperature Storage temperature Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute ...
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V ± ± ± ± Characteristics (V DD Parameter High-level input voltage Low-level input voltage High-level output current Low-level output current Input leakage current PCI interface High-level input voltage Low-level input voltage High-level output ...
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AC Characteristics PCI Interface See PCI local bus specification Revision 2.2. Serial ROM Interface See AT24C01A/02/04/08/16 Spec. Sheet. 34 Data Sheet S14793EJ1V0DS ...
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PACKAGE DRAWING 120-PIN PLASTIC TQFP (FINE PITCH) (14x14 120 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
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RECOMMENDED SOLDERING CONDITIONS The µ PD72850A should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For ...
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Data Sheet S14793EJ1V0DS 37 ...
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Data Sheet S14793EJ1V0DS ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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EEPROM and Firewarden are trademarks of NEC Corporation. • The information in this document is current as of November, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets ...