upd72872 Renesas Electronics Corporation., upd72872 Datasheet - Page 22

• Manufacturer Part Number: upd72872
• Description: Ieee1394 1-chip Ohci Host Controller
• Manufacturer: Renesas Electronics Corporation.

3.1.5 Offset_08
3.1.6 Offset_09
3.1.7 Offset_0C
The following cache line sizes are supported: 2, 4, 8, 16, 32, 64, and 128. All other values will be recognized as 0,
i.e. cache disabled.
3.1.8 Offset_0D
after it has acquired bus ownership and initiated a subsequent transaction.
3.1.9 Offset_0E
3.1.10 Offset_0F BIST Register
22
7-0
7-0
15-8
23-16
7-0
7-0
7-0
7-0
This register specifies a revision number assigned by NEC Corporation for the µ PD72872.
This register identifies the class code, sub-class code, and programming interface of the µ PD72872.
This register specifies the system cache line size, which is PC-host system dependent, in units of 32-bit words.
This register defines the maximum amount of time that the µ PD72872 is permitted to retain ownership of the bus
Bits
Bits
Bits
Bits
Bits
Bits
Revision ID Register
Class Code Register
Header Type Register
Cache Line Size Register
Latency Timer Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
Default value of 01H. It specifies the silicon revision. It will be incremented for subsequent
silicon revisions.
Constant value of 10H. It specifies an IEEE1394 OpenHCI-compliant Host Controller.
Constant value of 00H. It specifies an “IEEE1394” type.
Constant value of 0CH. It specifies a “Serial Bus Controller”.
Default value of 00H.
Default value of 00H. It specifies the number of PCI-bus clocks that the µ PD72872 may hold
the PCI bus as a bus-master.
Constant value of 00H. It specifies a single function device.
Constant value of 00H. It specifies whether the device is capable of Built-in Self Test.
Data Sheet S14793EJ1V0DS
Description
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