upd72872 Renesas Electronics Corporation., upd72872 Datasheet - Page 21

• Manufacturer Part Number: upd72872
• Description: Ieee1394 1-chip Ohci Host Controller
• Manufacturer: Renesas Electronics Corporation.

3.1.4 Offset_06
and “Write” are handled somewhat differently.
3-0
4
6,5
7
8
10,9
11
12
13
14
15
This register tracks the status information of PCI-bus related events which are relevant to the µ PD72872. “Read”
Bits
Status Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
Reserved Constant value of 0000.
New capabilities
Reserved Constant value of 00.
Fast back-to-back capable Constant value of 1. It indicates that the µ PD72872, as a target,
cannot accept fast back-to-back transactions when the transactions are not to the same agent.
Signaled parity error Default value of 0. It indicates the occurrence of any “Data Parity”.
DEVSEL timing Constant value of 01. These bits define the decode timing for DEVSEL.
Signaled target abort Default value of 0. This bit is set by a target device whenever it
terminates a transaction with “Target Abort”.
Received target abort Default value of 0. This bit is set by a master device whenever its
transaction is terminated with a “Target Abort”.
Received master abort
transaction is terminated with “Master Abort”. The µ PD72872 asserts “Master Abort” when a
transaction response exceeds the time allocated in the latency timer field.
Signaled system error Default value of 0. It indicates that the assertion of SERR by the
µ PD72872.
Received parity error Default value of 0. It indicates the occurrence of any PERR.
0: No parity detected (default)
1: Parity detected
0: Fast (1 cycle)
1: Medium (2 cycles)
2: Slow (3 cycles)
3: undefined
0: The µ PD72872 did not terminate a transaction with Target Abort
1: The µ PD72872 has terminated a transaction with Target Abort
0: The µ PD72872 has not received a Target Abort
1: The µ PD72872 has received a Target Abort from a bus-master
0: Transaction was not terminated with a Master Abort
1: Transaction has been terminated with a Master Abort
0: System error was not signaled
1: System error was signaled
0: No parity error was detected
1: Parity error was detected
Data Sheet S14793EJ1V0DS
Constant value of 1. It indicates the existence of the Capabilities List.
Default value of 0. This bit is set by a master device whenever its
Description
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