upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 185

• Manufacturer Part Number: upd78f0148m1gka1-9eu
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(3) Pulse width measurement with free-running counter and two capture registers
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
When 16-bit timer counter 0n (TM0n) is operated in free-running mode, it is possible to measure the pulse width
of the signal input to the TI00n pin.
When the rising or falling edge specified by bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n
(PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n
(CR01n) and an interrupt request signal (INTTM01n) is set.
Also, when the inverse edge to that of the capture operation is input into CR01n, the value of TM0n is taken into
16-bit timer capture/compare register 00n (CR00n).
Sampling is performed using the count clock cycle selected by prescaler mode register 0n (PRM0n), and a
capture operation is only performed when a valid level of the TI00n pin is detected twice, thus eliminating noise
with a short pulse width.
Figure 7-27. Control Register Settings for Pulse Width Measurement with Free-Running Counter and
n = 0:
n = 0, 1:
TMC0n
CRC0n
PRM0n
See the description of the respective control registers for details.
ES1n1
µ
µ
0/1
7
0
7
0
PD780143, 780144
PD780146, 780148, 78F0148
ES1n0
0/1
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
6
0
6
0
Two Capture Registers (with Rising Edge Specified)
(a) 16-bit timer mode control register 0n (TMC0n)
(b) Capture/compare control register 0n (CRC0n)
ES0n1
5
0
5
0
0
(c) Prescaler mode register 0n (PRM0n)
ES0n0
4
0
4
0
1
User’s Manual U15947EJ3V1UD
TMC0n3
0
3
0
3
0
TMC0n2
CRC0n2
1
1
2
0
TMC0n1
CRC0n1
PRM0n1
0/1
0/1
1
OVF0n
CRC0n0
PRM0n0
0/1
0
1
Free-running mode
Selects count clock (setting “11” is prohibited).
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
CR00n used as capture register
Captures to CR00n at inverse edge
to valid edge of TI00n.
CR01n used as capture register
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