upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 654

• Manufacturer Part Number: upd78f0148m1gka1-9eu
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

654
Serial
interface
UART6
Serial
interfaces
CSI10,
CSI11
Serial
interface
CSIA0
Function
Generation of
serial clock
Permissible
baud rate range
during reception
SOTB1n:
Transmit buffer
register 1n
SIO1n: Serial
I/O shift register
1n
CSIM10: Serial
operation mode
register 10
CSIC10: Serial
clock selection
register 10
CSIC11: Serial
clock selection
register 11
3-wire serial I/O
mode
Communication
operation
SO1n output
SIOA0: Serial
I/O shift register
0
CSIMA0: Serial
operation mode
specification
register 0
Details of
Function
Keep the baud rate error during transmission to within the permissible error
range at the reception destination.
Make sure that the baud rate error during reception satisfies the range shown in
(4) Permissible baud rate range during reception.
Make sure that the baud rate error during reception is within the permissible error
range, by using the calculation expression shown below.
Do not access SOTB1n when CSOT1n = 1 (during serial communication).
The SSI11 pin can be used in the slave mode. For details of the
transmission/reception operation, see 16.4.2 (2) Communication operation.
Do not access SIO1n when CSOT1n = 1 (during serial communication).
The SSI11 pin can be used in the slave mode. For details of the reception
operation, see 16.4.2 (2) Communication operation.
Be sure to clear bit 5 to 0.
When the internal oscillation clock is selected as the clock supplied to the CPU,
the clock of the internal oscillator is divided and supplied as the serial clock. At
this time, the operation of serial interface CSI10 is not guaranteed.
Do not write to CSIC10 while CSIE10 = 1 (operation enabled).
Clear CKP10 to 0 to use P10/SCK10/TxD0, P11/SI10/RxD0, and P12/SO10 as
general-purpose port pins.
The phase type of the data clock is type 1 after reset.
When the internal oscillation clock is selected as the clock supplied to the CPU,
the clock of the internal oscillator is divided and supplied as the serial clock. At
this time, the operation of serial interface CSI11 is not guaranteed.
Do not write to CSIC11 while CSIE11 = 1 (operation enabled).
Clear CKP11 to 0 to use P02/SO11, P03/SI11, and P04/SCK11 as general-
purpose port pins.
The phase type of the data clock is type 1 after reset.
Take relationship with the other party of communication when setting the port
mode register and port register.
Do not access the control register and data register when CSOT1n = 1 (during
serial communication).
When using serial interface CSI11, wait for the duration of at least one clock
before the clock operation is started to change the level of the SSI11 pin in the
slave mode; otherwise, malfunctioning may occur.
If a value is written to TRMD1n, DAP1n, and DIR1n, the output value of SO1n
changes.
A communication operation is started by writing to SIOA0. Consequently, when
transmission is disabled (bit 3 (TXEA0) of CSIMA0 = 0), write dummy data to the
SIOA0 register to start the communication operation, and then perform a receive
operation.
Do not write data to SIOA0 while the automatic transmit/receive function is
operating.
When CSIAE0 = 0, the buffer RAM cannot be accessed.
When CSIAE0 is changed from 1 to 0, the registers and bits mentioned in Note
above are asynchronously initialized. To set CSIAE0 = 1 again, be sure to re-set
the initialized registers.
When CSIAE0 is re-set to 1 after CSIAE0 is changed from 1 to 0, it is not
guaranteed that the value of the buffer RAM will be retained.
APPENDIX D LIST OF CAUTIONS
User’s Manual U15947EJ3V1UD
Cautions
p. 356
p. 356
p. 356
p. 356
p. 359
p. 362
p. 362
p. 368
p. 372
p. 372
p. 373
p. 373
p. 373
p. 344
p. 344
p. 346
p. 351
p. 351
p. 351
p. 351
p. 352
p. 355
p. 355
p. 355
p. 355
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