upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 646

• Manufacturer Part Number: upd78f0148m1gka1-9eu
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

646
16-bit
timer/
event
counters
00, 01
(TM00,
TM01)
8-bit
timer/
event
counters
50, 51
(TM50,
TM51)
8-bit
timers H0,
H1
(TMH0,
TMH1)
Function
Edge detection
CR5n: 8-bit
timer compare
register 5n
TCL50: Timer
clock selection
register 50
TCL51: Timer
clock selection
register 51
TMC5n: 8-bit
timer mode
control register
5n
Interval
timer/square-
wave output
PWM output
Timer start error An error of up to one clock may occur in the time required for a match signal to be
CMP0n: 8-bit
timer H
compare
register 0n
CMP1n: 8-bit
timer H
compare
register 1n
Details of
Function
If the TI00n or TI01n pin is high level immediately after system reset and the rising
edge or both the rising and falling edges are specified as the valid edge of the
TI00n or TI01n pin to enable the 16-bit timer counter 0n (TM0n) operation, a rising
edge is detected immediately after the operation is enabled. Be careful therefore
when pulling up the TI00n or TI01n pin. However, if the TI00n pin or TI01n pin is
high level when re-enabling operation after the operation has been stopped, the
rising edge is not detected.
The sampling clock used to eliminate noise differs when the TI00n valid edge is
used as the count clock and when it is used as a capture trigger. In the former
case, the count clock is f
prescaler mode register 0n (PRM0n). The capture operation is only performed
when a valid level is detected twice by sampling the valid edge, thus eliminating
noise with a short pulse width.
In the mode in which clear & start occurs on a match of TM5n and CR5n (TMC5n6
= 0), do not write other values to CR5n during operation.
In PWM mode, make the CR5n rewrite interval 3 count clocks of the count clock
(clock selected by TCL5n) or more.
When the internal oscillation clock is selected as the clock to be supplied to the
CPU, the clock of the internal oscillator is divided and supplied as the count clock.
If the count clock is the internal oscillation clock, the operation of 8-bit timer/event
counter 50 is not guaranteed.
When rewriting TCL50 to other data, stop the timer operation beforehand.
Be sure to clear bits 3 to 7 to 0.
When the internal oscillation clock is selected as the clock to be supplied to the
CPU, the clock of the internal oscillator is divided and supplied as the count clock.
If the count clock is the internal oscillation clock, the operation of 8-bit timer/event
counter 51 is not guaranteed.
When rewriting TCL51 to other data, stop the timer operation beforehand.
Be sure to clear bits 3 to 7 to 0.
The settings of LVS5n and LVR5n are valid in other than PWM mode.
Perform <1> to <4> below in the following order, not at the same time.
<1> Set TMC5n1, TMC5n6: Operation mode setting
<2> Set TOE5n to enable output: Timer output enable
<3> Set LVS5n, LVR5n (see Caution 1): Timer F/F setting
<4> Set TCE5n
Stop operation before rewriting TMC5n6.
Do not write other values to CR5n during operation.
In PWM mode, make the CR5n rewrite interval 3 count clocks of the count clock
(clock selected by TCL5n) or more.
When reading from CR5n between <1> and <2> in Figure 8-15, the value read
differs from the actual value (read value: M, actual value of CR5n: N).
generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50,
TM51) are started asynchronously to the count clock.
CMP0n cannot be rewritten during timer count operation.
In the PWM output mode and carrier generator mode, be sure to set CMP1n when
starting the timer count operation (TMHEn = 1) after the timer count operation was
stopped (TMHEn = 0) (be sure to set again even if setting the same value to
CMP1n).
APPENDIX D LIST OF CAUTIONS
User’s Manual U15947EJ3V1UD
X
, and in the latter case the count clock is selected by
Cautions
p. 205
p. 206
p. 200
p. 200
p. 204
p. 204
p. 205
p. 205
p. 206
p. 206
p. 208
p. 208
p. 208
pp. 210,
213
p. 214
p. 217
p. 218
p. 222
p. 222
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