upd78f0148m1gka1-9eu Renesas Electronics Corporation., upd78f0148m1gka1-9eu Datasheet - Page 657

• Manufacturer Part Number: upd78f0148m1gka1-9eu
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Interrupt
Key
interrupt
function
Standby
function
Function
IF0L, IF0H, IF1L,
IF1H: Interrupt
request flag
registers
MK1H: Interrupt
mask flag
register
PR1H: Priority
specification flag
register
EGP, EGN:
External interrupt
rising/falling
edge enable
registers
Software
interrupt request
acknowledgment
Interrupt request
hold
KRM: Key return
mode register
STOP mode,
HALT mode
STOP mode
Details of
Function
−
Use the 1-bit memory manipulation instruction (CLR1) for manipulating the flag of
the interrupt request flag register. A 1-bit manipulation instruction such as “IF0L.0
= 0;” and “_asm(“clr1 IF0L, 0”);” should be used when describing in C language,
because assembly instructions after compilation must be 1-bit memory
manipulation instructions (CLR1).
If an 8-bit memory manipulation instruction “IF0L & = 0xfe;” is described in C
language, for example, it is converted to the following three assembly instructions
after compilation:
mov a, IF0L
and
mov IF0L, a
In this case, at the timing between “mov a, IF0L” and “mov IF0L, a”, if the request
flag of another bit of the identical interrupt request flag register (IF0L) is set to 1,
it is cleared to 0 by “mov IF0L, a”. Therefore, care must be exercised when using
an 8-bit memory manipulation instruction in C language.
Be sure to set bits 6 and 7 of MK1H to 1 and clear bit 5 to 0.
Be sure to set bits 5 to 7 of PR1H to 1.
Select the port mode after clearing EGPn and EGNn to 0 because an edge may
be detected when the external interrupt function is switched to the port function.
Do not use the RETI instruction for restoring from the software interrupt.
The BRK instruction is not one of the above-listed interrupt request hold
instructions. However, the software interrupt activated by executing the BRK
instruction causes the IE flag to be cleared to 0. Therefore, even if a maskable
interrupt request is generated during execution of the BRK instruction, the
interrupt request is not acknowledged.
If any of the KRM0 to KRM7 bits used is set to 1, set bits 0 to 7 (PU70 to PU77)
of the corresponding pull-up resistor register 7 (PU7) to 1.
If KRM is changed, the interrupt request flag may be set. Therefore, disable
interrupts and then change the KRM register. After that, clear the interrupt
request flag and then enable interrupts.
The bits not used in the key interrupt mode can be used as normal ports.
The RSTOP setting is valid only when “Can be stopped by software” is set for
internal oscillator by a mask option.
STOP mode can be used only when CPU is operating on the X1 input clock or
internal oscillation clock. HALT mode can be used when CPU is operating on the
X1 input clock, internal oscillation clock, or subsystem clock. However, when the
STOP instruction is executed during internal oscillation clock operation, the X1
oscillator stops, but internal oscillator does not stop.
When shifting to the STOP mode, be sure to stop the peripheral hardware
operation before executing STOP instruction.
The following sequence is recommended for operating current reduction of the
A/D converter when the standby function is used: First clear bit 7 (ADCS) of the
A/D converter mode register (ADM) to 0 to stop the A/D conversion operation,
and then execute the HALT or STOP instruction.
If the internal oscillator is operating before the STOP mode is set, oscillation of
the internal oscillation clock cannot be stopped in the STOP mode. However,
when the internal oscillation clock is used as the CPU clock, the CPU operation is
stopped for 17/f
a, #0FEH
APPENDIX D LIST OF CAUTIONS
User’s Manual U15947EJ3V1UD
R
(s) after STOP mode is released.
Cautions
p. 426
p. 426
p. 427
p. 428
p. 432
p. 436
p. 438
p. 438
p. 438
p. 439
p. 440
p. 440
p. 440
p. 440
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