z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 218

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
Each interrupt source other than the baud rate generator interrupt has an associated bit in
the I2CISTAT register, which clears automatically when software reads the register or
performs some other task such as reading or writing the data register.
Transmit interrupts
Transmit interrupts (
•
•
Writing to the I
Receive interrupts
Receive interrupts (
received by the I
register. If the RDRF interrupt is not serviced prior to the completion of the next receive
byte, the I
is cleared to prevent receive overruns. A receive interrupt does not occur when a Slave
receives an address byte or for data bytes following a Slave address that did not match. An
exception is if the interactive receive mode (
which case receive interrupts occur for all receive address and data bytes in Slave mode.
Slave Address Match interrupts
Slave address match interrupts (
is in Slave mode and an address is received which matches the unique Slave address. The
General Call Address (0000_0000) and STARTBYTE (0000_0001) are recognized if the
GCE
register to determine if the transaction is a read or write transaction. The General Call
Address and STARTBYTE addresses are also distinguished by the
address (
on the unique Slave address or the General Call/STARTBYTE address. The
automatically when the I2CISTAT register is read.
If configured using the
addressing, the most significant 7 bits of the first byte of the transaction are compared
against the
addressing, the first byte of the transaction is compared against {11110,
and the second byte is compared against
The transmit data register is empty and the
The I
– The first bit of a 10-bit address is shifted out.
– The first bit of the final byte of an address is shifted out and the
– The first bit of a data byte is shifted out.
bit = 1 in the I2CMODE register. Software verifies the
2
GCA
C Controller is enabled, with any one of the following:
2
C Controller holds SCL Low during the last data bit of the next byte until
SLA[6:0]
) bit of the I2CISTAT register indicates whether the address match occurred
2
C Data register always clears the
2
C Controller. The
RDRF
TDRE
bits of the Slave Address register. If configured for 10-bit slave
MODE[1:0]
bit =
bit = 1 in I2CISTAT) occur under the following conditions:
P R E L I M I N A R Y
1
SAM
in I2CISTAT) occur when a byte of data has been
RDRF
field of the I
bit =
SLA[7:0]
bit is cleared by reading from the I
1
in I2CISTAT) occur when the I
IRM
TXI
) bit is set in the I2CMODE register in
2
C Mode register for 7-bit slave
TRDE
bit = 1 in the I
.
bit to 0.
RD
I2C Master/Slave Controller
bit in the I2CISTAT
Product Specification
2
ZNEO
RD
C Control register.
RD
bit. The general call
SLA[9:8]
bit is deasserted.
™
2
SAM
Z16F Series
C Controller
2
C Data
bit clears
,R/W}
RDRF
204