z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 318

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
Reading Memory CRC
Breakpoints
been received during a write operation. A debug read cycle will occur when the transmit-
ter is empty during a read operation.
Data read from or written to the OCD occurs one byte at a time. Therefore, memory read
and write operations occur one byte at a time. Operations that occur on multi-byte words
does not occur concurrently.
Since the ZNEO device has such a large memory space and the debug interface is serial,
reading massive amounts of data during debugging is time consuming. The OCD hard-
ware has the capability of calculating a cyclic redundancy check (CRC) on memory to
allow memory caching mechanisms to be used by the host debugging software. This CRC
verifies that the contents of a memory cache has not changed.
When the read CRC command is issued, the OCD hardware steals the CPU bus during the
entire read operation. The length of time it takes to generate the CRC is equal to the
amount of time it takes to read the memory used in the CRC calculation.
The OCD hardware also has the capability of returning separate CRCs for each 4K block
of memory. This is used by software to determine the portions of memory, which have
been modified when the cache for a large block of memory is invalidated.
Software Breakpoints
Breakpoints are generated when the CPU executes the
enabled. If breakpoints are not enabled, the
exception vector and set the illegal instruction status bit.
If a Breakpoint is generated, the OCD is configured to automatically enter Debug Halt
mode or to just loop on the instruction. If the OCD is configured to loop on the instruction,
the CPU is still able to service DMA and interrupt requests in the background. Software
polls the
Breakpoint.
Hardware Breakpoint
There are four hardware breakpoints on the ZNEO Device. When enabled, a breakpoint is
generated when the program counter matches the value in the breakpoint register, or when
a memory access occurs at the address in the breakpoint register. A data watchpoint
watches a range of addresses by selecting how many lower address bits are ignored.
DBGBRK
bit of the DBGCTL register to determine if the OCD has reached a
P R E L I M I N A R Y
BRK
instruction will vector to the system
BRK
instruction and breakpoints are
Product Specification
ZNEO
On-Chip Debugger
™
Z16F Series
304