z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 97

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
Note:
Interrupt Vectors and Priority
System Exceptions
Interrupt Assertion
For illegal instructions the program counter and flags is only pushed on the stack once.
If the associated exception bit is not Reset, the program counter and flags will not get
pushed again.
•
•
•
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest
priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all the
interrupts are enabled with identical interrupt priority (for example, all interrupts enabled
as Level 2 interrupts), the interrupt priority is assigned from highest to lowest as specified
in
interrupts, which in turn, always have higher priority than Level 1 interrupts. Within each
interrupt priority levels (Level 1, Level 2, or Level 3), priority is assigned as specified in
Table
System Exceptions are generated for stack overflow, illegal instructions, divide-by-zero,
and divide overflow, etc. The System Exceptions are not affected by the IRQE and share a
single vector.
Each exception has a bit in the system exception status register. When a system exception
occurs it pushes the program counter and the flags on the stack, fetches the system
exception vector from 000008H (similar to a IRQ) and the bit associated with that
exception is set in the status register. Additional exceptions from the same source are
blocked until the status bit of the particular exception is cleared by writing 1 to that status
bit. Other types of exceptions occur while servicing an exception. When this happens the
processor again vectors to the system exception vector and sets the associated exception
status bit. The service routine would then have to respond to the new exception.
Interrupt sources assert their interrupt requests for only a single system clock period
(single pulse). When the interrupt request is acknowledged by the ZNEO CPU, the
corresponding bit in the interrupt request register is cleared until the next interrupt occurs.
Writing 1 to the corresponding bit in the interrupt request register clears the interrupt
request.
Program code generates interrupts directly. Writing a 1 to the appropriate bit in the
interrupt request set register triggers an interrupt (assuming that interrupts are enabled).
When the interrupt request is acknowledged by the ZNEO CPU, the bit in the interrupt
request register is automatically cleared to 0.
Table 39
Reset
Execution of a
All System Exceptions
39. Reset and System Exceptions have the highest priority.
on page 80. Level 3 interrupts always have higher priority than Level 2
TRAP
instruction
P R E L I M I N A R Y
Product Specification
ZNEO
Interrupt Controller
™
Z16F Series
83