mk2069-04 Integrated Device Technology, mk2069-04 Datasheet - Page 18

• Manufacturer Part Number: mk2069-04
• Description: Vcxo-based Universal Clock Translator
• Manufacturer: Integrated Device Technology

AC Electrical Characteristics
IDT™ / ICS™ VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Crystal Frequency Range
(Note 1)
VCXO Crystal Pull Range
VCXO Crystal Free-Run
Frequency (Note 2)
Input Clock Frequency when
RPV Divider = 8 (Note 3)
Input Clock Frequency when
RPV Divider = 1 (Note 3, 4)
Input Clock Pulse Width
VCXO PLL Phase Detector
Frequency (Note 3)
VCXO PLL Phase Detector Jitter
Tolerance
Translator PLL VCO Frequency
Timing Jitter, Filtered
500 Hz-1.3 MHz (OC-3)
Timing Jitter, Filtered
65 kHz-5 MHz (OC-3)
Timing Jitter, Filtered
1 kHz-5 MHz (OC-12)
Timing Jitter, Filtered
250 kHz-5 MHz (OC-12)
Output Duty Cycle (% high time),
VCLK when SV Divider = 1
Output Duty Cycle (% high time),
VCLK when SV Divider > 1,
TCLK
Output High Time, RCLK
(Note 5)
Parameter
Symbol
f
XTAL
t
t
t
t
t
t
t
f
f
f
t
t
OJf
OJf
OJf
OJf
PD
f
OD
OD
OH
XP
XF
JT
f
f
ID
V
I
I
Using recommended
crystal
Using recommended
crystal
Input reference = 0 Hz
Positive or Negative
Pulse
1 UI = phase detector
period
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
Measured at VDD/2,
C
Measured at VDD/2,
C
Measured at VDD/2,
C
L
L
L
=15 pF
=15 pF
=15 pF
Conditions
18
0.008
0.002
0.001
±115
Min.
13.5
-300
10
40
40
44
Period
VCLK
Typ.
±150
-150
105
0.4
0.5
95
85
80
50
50
VCXO AND SYNTHESIZER
MK2069-04
Max. Units
170
160
320
27
27
60
65
MHz
MHz
MHz
nsec
MHz
MHz
ppm
ppm
UI
ps
ps
ps
ps
%
%
REV G 090905