mk2069-04 Integrated Device Technology, mk2069-04 Datasheet - Page 9

• Manufacturer Part Number: mk2069-04
• Description: Vcxo-based Universal Clock Translator
• Manufacturer: Integrated Device Technology

Setting the RPV, RV, FV and SV Divider Values
As shown in the loop bandwidth and damping factor
equations on page 6, or by using the filter response software
available from ICS, increasing FV or SV decreases both
bandwidth and damping factor. Many applications require
that SV = 1. In these cases, one way to decrease loop
bandwidth is to increase the value of FV, which is
accompanied by an increase in the value of RPV and/or RV
Example Loop Filter Component Value
Loop Filter Capacitor Type
Loop filters must use specific types of capacitors.
Recommendations for these capacitors can be found at
www.icst.com.
Input Phase Compensation Circuit
The VCXO PLL includes a special input clock phase
compensation circuit. It is used when changing the phase of
the input clock, which might occur when selecting a new
IDT™ / ICS™ VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
Frequency
19.44 MHz
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
Detector
Phase
8 kHz
8 kHz
8 kHz
Notes:
1) This filter configuration assures a passband ripple compliant with Bellcore GR-1244-CORE to satisfy wander
transfer requirements (<0.2 dB ripple is required) of a network node. It can be used following a system synchronizer
such as the MT9045 to provide clock jitter attenuation while maintaining Stratum 3 compliance. A 155.52 MHz TCLK
output generated with the VCXO PLL configuration will be OC-3 and OC-12 timing jitter compliant.
2) This is a reduced cost and size variant of the above filter, due to the decreased size of C
GR-1244-CORE compliance is not needed.
3) This configuration is used to generate a DS3 clock of 44.768 MHz at the TCLK output. This configuration is
GR-1244-CORE compliant when used following a system synchronizer.
4) Lowering the phase detector frequency, by increasing the value of the RPV and/or RV dividers and the FV divider,
will lower the loop bandwidth and/or decrease the size of C
in the VCXO PLL
22.368
(MHz)
19.44
19.44
19.44
Freq
Xtal
Div
SV
1
1
1
1
22.368 2796 1 MΩ 680 kΩ
VCLK
(MHz)
19.44 2430 1 MΩ 560 kΩ
19.44 2430 1 MΩ 560 kΩ 0.1 µF 4.7 nF 27 Hz
19.44
128
Div
FV
1 MΩ
R
SET
27 kΩ
R
S
1 µF
1 µF
1 µF
C
S
9
to maintain the same PLL frequency multiplication ratio.
However, the phase detector frequency, F
be considered. F
by the value of the RPV x RV. F
20x the loop bandwidth to prevent loop modulation (phase
noise) by the phase detector frequency. The phase detector
jitter tolerance limit (use 0.4UI) and input phase noise
frequency aliasing should be considerations as well.
reference input through the use of an external clock
multiplexer.
The phase compensation circuit allows the VCXO PLL to
quickly lock to the new input clock phase without producing
extra clock cycles or clock wander, assuming the new clock
is at the same frequency.
Input pin CLR controls the phase compensation circuit. CLR
must remain high for normal operation. When used in
4.7 nF 22 Hz
4.7 nF 20 Hz
47 nF
S
C
for the same damping factor.
P
(-3dB)
25 Hz
Loop
BW
Damp.
Loop
0.85
4.0
1.4
4.5
PD
is equal to the input frequency divided
0.15dB at 1Hz
0.12dB at 1Hz
1.2dB at 6Hz
1.8dB at 8Hz
Passband
Peaking
PD
VCXO AND SYNTHESIZER
should be typically at least
S
. It is useful when
MK2069-04
Note
1
2
3
4
PD
, also needs to
REV G 090905