mk2069-04 Integrated Device Technology, mk2069-04 Datasheet - Page 6

• Manufacturer Part Number: mk2069-04
• Description: Vcxo-based Universal Clock Translator
• Manufacturer: Integrated Device Technology

the pullable range of the crystal. This is guaranteed to be
±115 ppm minimum. This tracking range in ppm also applies
to the input clock and all clock outputs if the device is to
remain frequency locked to the input, which is required for
normal operation.
Setting TCLK Output Frequency
The clock frequency of TCLK is determined by:
The frequency range of TCLK is set by the operational range
of the internal VCO circuit and the output divider selections:
A higher VCO frequency will generally produce lower phase
noise and therefore is preferred.
MK2069-04 Loop Response and JItter
The MK2069-04 will reduce the transfer of phase jitter
existing on the input reference clock to the output clock. This
operation is known as jitter attenuation. The low-pass
frequency response of the VCXO PLL loop is the
mechanism that provides input jitter attenuation. Clock jitter,
more accurately called phase jitter, is the overall instability
of the clock period which can be measured in the time
domain using an oscilloscope, for instance. Jitter is
comprised of phase noise which can be represented in the
frequency domain. The phase noise of the input reference
clock is attenuated according to the VCXO PLL low-pass
frequency response curve. The response curve, and thus
the jitter attenuation characteristics, can be established
IDT™ / ICS™ VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
Where:
Where:
f(TCLK)
f(TCLK)
FT Divider = 2, 4, 6, 8, 10, 12, 14 or 16
f(VCO) = 40 to 320 MHz
ST Divider = 2,4,8 or 16
Attenuation Characteristics
=
=
FT Divider
---------------------- -
ST Divider
f(VCO)
×
f(VCLK)
6
through the selection of external MK2069-04 passive
components and other device setting as explained in the
following section.
Setting the VCXO PLL Loop Response.
The VCXO PLL loop response is determined both by fixed
device characteristics and by variables set by the user. This
includes the values of R
External VCXO PLL Components figure on this page.
The VCXO PLL loop bandwidth is approximated by:
The above equation calculates the “normalized” loop
bandwidth (denoted as “NBW”) which is approximately
equal to the - 3dB bandwidth. NBW does not take into
account the effects of damping factor or the second pole
imposed by C
approximation of filter performance.
To prevent jitter on VCLK due to modulation of the VCXO
PLL by the phase detector frequency, the following general
rule should be observed:
.
NBW(VCO PLL)
DF(VCLK)
The PLL loop damping factor is determined by:
NBW(VCO PLL)
Where:
R
I
K
SV Divider = 1,2,12 or 16
FV Divider = 1 to 4096
CP
O
S
= Value of resistor R
= VCXO Gain in Hz/V
= Charge pump current in amps
=
(see table on page 7)
(see table on page 8)
P
R
----- -
. It does, however, provide a useful
2
S
≤
×
f(Phase Detector)
-------------------------------------- -
=
------------------------------------------------------------- -
SV Divider
-------------------------------------------------------------------------- -
2π SV Divider
S
, C
×
I
CP
20
S
, C
×
R
P
VCXO AND SYNTHESIZER
C
S
S
×
×
S
and R
in loop filter in Ohms
FV Divider
×
MK2069-04
I
CP
K
O
×
×
SET
FV Divider
K
O
as shown in the
REV G 090905