el4511 Intersil Corporation, el4511 Datasheet - Page 17

• Manufacturer Part Number: el4511
• Description: Super Sync Separator
• Manufacturer: Intersil Corporation

Video Format Switching
The part should be powered down for at least 500µs to reset
the internal registers when the input video signal is switched
from one video format to another video format. It is possible
the part will generate wrong outputs if it is not powered down
between two different input video signals.
USE OF THE POWER DOWN FUNCTION
The Power down pin (pin 4) can be used to hard reset the
internal circuit of the EL4511. To disable the internal circuit,
just apply a 5V to the power down pin. To enable the internal
circuit, just apply a 0V to the power down pin.
The SYNCLOCK pin 3 minus edge can be used to generate
a 5V 500µs pulse to the PDWN pin 4 to reset the internal
digital registers automatically when the video input has a
changed video format.
Horizontal Rate Acquisition Oscillator
This oscillator is frequency locked to 512 times the horizontal
rate. This clock signal generates the timing and gating
signals that are employed internally by the EL4511. This
operation is entirely automatic and requires no input from the
external circuitry or microprocessor.
(Serial Mode) It is possible to gain access to this oscillator
O/P by changing the assignment of pin 2 (V
(ODD/EVEN).
Register 6, bits 7:6 make this selection; see Table 1 for
allocations.
Sync_Lock pin
CmuxCtrl
b7 b6
Reg6
0 0
0 1
1 0
1 1
TABLE 1. ACQUISITION CLOCK MULTIPLEXER
20K
R1
R1
Normal Operation
Clock multiplexed onto Odd/Even (pin 23)
Clock multiplexed onto V
Reserved
VDD
C1
C1
0.022u
17
10K
R2
Q1
Q1
ACTION
R3
100K
0
MPS3906
MPS3906
BLANK
BLANK
(pin 2)
POWERDOWN
) or pin 23
EL4511
(Serial Mode) The oscillator frequency is adjusted at the
beginning of the line. At the time of frequency adjustment the
clock O/P may have a phase discontinuity.
Advanced Sync Separator
Once the line rate has been determined, the signal can be
analyzed by the advanced sync separator. This has been
designed to be compatible with a wide range of video
standards, operating with horizontal line rates up to 150kHz.
PAL/NTSC/SECAM; HDTV, including bi-level and tri-level
sync Standards and computer display syncs. The EL4511
can be programmed to disable the detection of either bi-level
or tri-level sync signals or to prioritize the detection of one
sync signal type over the other.
If the vertical sync input pin, VERTIN, is enabled, the EL4511
will automatically detect whether a valid signal is present on
that pin, and incorporate that signal into the algorithm.
Otherwise, the input signal on which the horizontal sync was
detected will be treated as a composite sync. The sync
separator also includes a qualification scheme which rejects
high frequency noise and other video artifacts, such as color
burst. The horizontal line rate is automatically acquired from
the signal (see above.) A digital filter is included in the signal
path to remove noise and glitches; this may be removed if
the extra delay it incurs needs to be removed. (Serial Mode)
Setting register 2, bit 4 to Low will remove the filter.
After the signal has been identified and the qualification
process is complete, the SYNCLOCK pin will go high and
the output waveforms will be enabled. (Serial Mode) These
may be enabled all the time by setting register 1, bit 6 to a
high state. This can help noisy and varying signals as the
revalidation does not have to take place before the signals
are available at the outputs, See Figures 4 through 7 for
examples of various types of input signal.
Part of the signal recognition algorithm uses the number of
horizontal lines between vertical pulses. A counter is clocked
by the Hclock, this counter is also used to generate vertical
timing pulses. (Serial Mode) This count information is
available via the serial I/F; this is a 12 bit number.
(Serial Mode) The lines per frame count is available at
register 8, bits 7:4 for the MSBs; the LSBs are available at
register 7, bits 7:0. Register 8, bit 2 indicates that the
lines/frame counter has been updated when it is high.
This counter also generates the V
look up table, the default blanking is based on number of
lines in the field. (Serial Mode) This operation may be
disabled by setting register 3, bit 7 to a low. As this is
dependent on application and product usage, this may be
modified. Register 3, bits 6:0 will set the number of
horizontal lines after VERTOUT leading edge. Register 4,
bits 7:4 sets the number of lines before the VERTOUT
leading edge.
BLANK
waveform. Using a
July 21, 2005
FN7009.7