el4511 Intersil Corporation, el4511 Datasheet - Page 18

• Manufacturer Part Number: el4511
• Description: Super Sync Separator
• Manufacturer: Intersil Corporation

Video Lock and Level Indicators
Loss of video signal can be detected by monitoring the
SYNCLOCK pin 3. This pin goes high once the sync
separator has detected a valid sync signal and goes low if
this signal is lost for more than 20 successive lines. (Serial
Mode) This signal is also available at register 14 pin 5. Other
lock acquisition signals available from the system are listed
in Table 4.
The sync tip amplitude is buffered with a nominal gain of
2.15 to produce a positive, ground-referenced signal on the
LEVEL pin. This output can be used for AGC applications.
Decode Mode
In order to allow more flexibility when operating without a
serial interface, the XTAL and XTALN pins are decoded by
default to enable four control modes. These modes could be
used to over-ride sync type used. See Table 2 for details.
(Serial Mode) The all-signal type allowed mode is the same
as the default mode when the crystal oscillator is enabled
(set bit 6 of Reg9 to 1) except the countsPerField function is
disabled in Reg13 and Reg14.
The bi-level mode is for bi-level sync only, such as NTSC
and PAL. The tri-level mode is for tri-level sync only, such as
HDTV signals. The VGA only mode is for computer digital
types of signals signal only.
Register9
ENXTAL
b 6
0
0
0
0
1
TABLE 2. MODE CONTROL USING PINS 1 & 24
PIN 1
XTAL
0
0
1
1
X
XTALN
PIN 24
X
0
1
0
1
18
CONTROL
Register1
b5 b4 b3
0
0
1
1
Serial I/F
MODE
Set by
0
1
0
1
0
1
1
1
All signals
enabled
Tri-Level Only
Bi-Level Only
VGA only
Crystal Oscillator
is operational
DESCRIPTION
EL4511
SYNCS
SYNCS
Applications Examples
The following examples show how a system may be
configured to operate the EL4511.
Application 1 (minimum circuitry application)
In this example, the requirement is for vertical and horizontal
timing to be generated from either an NTSC/PAL composite
video waveform, or a computer generated image with
separate TTL level syncs.
The EL4511 has the advantage that the sync separation is
carried out over a wide frequency range without the need to
adjust "R
separators.
As there is no Microcontroller connected in this example,
there is no need for a XTAL at pins 1 & 24. These pins are
tied low, this enables the EL4511 to check for either type of
input signal (See Table 2 for details.)
The internal pull-up resistors on XTAL & XTALN are very
high, these pins should use 10kΩ pull-up/down to operate
when not using a crystal.
By default, the EL4511 will wake up with Register 9, bit 6 set
to Low. This will allow the use of logic levels on pins 1 & 24
to drive register1, bits 5:3 and register 2 bit 0 into the
combinations shown in Table 2.
(Serial Mode) To define the mode through the serial
interface, the register 9, bit 6 must be set to High, the logic
levels on pins 1 & 24 are no longer valid; (most likely now
being an AC signal for the reference clock).
HORIZ
VERT
TTL
TTL
4.7µF
75Ω
75Ω
75Ω
SET
0.1µF
+
FIGURE 8. APPLICATIONS DRAWING 1
10kΩ
" as required by earlier generations of sync
100nF
10
24
11
9
4
1
HIN
VERTIN
SYNCIN
PDWN
XTAL
XTALN
EL4511
+5V
VERTOUT
GNDA2
HOUT
16
22
VERT
TIMING TO
SYSTEM
21
HORIZ
TIMING TO
SYSTEM
July 21, 2005
FN7009.7
0.1µF
+5V