el4511 Intersil Corporation, el4511 Datasheet - Page 23

• Manufacturer Part Number: el4511
• Description: Super Sync Separator
• Manufacturer: Intersil Corporation

REGISTER
NUMBER
16
REGISTER
SDENB
SDENB
SDA
SCL
SDA
SCL
BIT
7:6
5
4
3
2
1
0
4
3
td(SCL)
td(SCL)
START
START
“0”=WRITE
“I”=READ
CountsPerField <9:8>
SyncLock
CPFValid
SetBiLevel
VinSyncDet
VinPolarity
HPolarity
Oscillator Settings Observe 2
RateLocked
ALOS
WRITE TO REGISTER OF EL4511 (WRITE INDICATED WITH ADDRESS = 0XXXXXXX)
READ FROM REGISTER OF EL4511 (READ INDICATED WITH ADDRESS = 1XXXXXXX)
1
0
23
TABLE 5. SERIAL INTERFACE REGISTER BIT ALLOCATIONS (Continued)
t(SCL)HI t(SCL)LO
t(SCL)HI t(SCL)LO
SIGNAL NAME
REGISTER ADDRESS 7 BITS
REGISTER ADDRESS 7 BITS
FIGURE 11. SERIAL INTERFACE TIMING DIAGRAM
SETUP
SETUP
t(SDA)
t(SDA)
(1/F)*SCL
(1/F)*SCL
t(SDA)
HOLD
t(SDA)
HOLD
TYPE
EL4511
R
td(SDA)OUT
RESET
VALUE
D7
-
-
-
-
-
-
-
-
INPUT DATA 8 BITS
Crystal clock periods per field: Bits 9:8. (see description)
As sync lock pin.
Counts per field valid. Set L if read occurs during an update.
Lo: Tri-level mode; Hi: Bi-level mode.
Indicates vertical sync on VERTIN successfully acquired.
VERTIN polarity setting: Observe.
HIN polarity setting: Observe.
Indicates line rate successfully acquired.
Analog loss of signal, measured via S/H. H indicates analog
signal amplitude is below threshold.
OUTPUT DATA 8 BITS
DESCRIPTION AND COMMENTS
LSB
16
16
D0
t(SDENB)
IDLE
td(SDENB)STOP
td(SDA)
OFF
t(SDENB)
IDLE
td(SDENB)
July 21, 2005
FN7009.7