m41t81 STMicroelectronics, m41t81 Datasheet - Page 12

• Manufacturer Part Number: m41t81
• Description: Serial Access Real-time Clock With Alarms
• Manufacturer: STMicroelectronics

Operation
2.3
2.4
12/30
WRITE mode
In this mode the master transmitter transmits to the M41T81 slave receiver. Bus protocol is
shown in
(R/W=0) is placed on the bus and indicates to the addressed device that word address “An”
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
address location on the reception of an acknowledge clock. The M41T81 slave receiver will
send an acknowledge clock to the master transmitter after it has received the slave address
see
byte.
Data retention mode
With valid V
WRITE Cycles. Should the supply voltage decay, the power input will be switched from the
V
At this time the clock registers will be maintained by the attached battery supply. On power-
up, when V
on page
For a further, more detailed review of lifetime calculations, please see Application Note
AN1012.
Figure 9.
CC
Figure 6 on page 11
pin to the battery when V
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
23,
Figure 9 on page
CC
CC
Table 11 on page
WRITE mode sequence
returns to a nominal value, write protection continues for t
applied, the M41T81 can be accessed as described above with READ or
S
ADDRESS
S
SLAVE
ADDRESS
SLAVE
and again after it has received the word address and each data
12. Following the START condition and slave address, a logic '0'
CC
ADDRESS (An)
24).
WORD
falls below the Battery Back-up Switchover Voltage (V
DATA n
DATA n
DATA n+1
DATA n+1
DATA n+X
AI00591
rec
DATA n+X
(see
P
Figure 10
AI00895
M41T81
P
SO
).