ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 137

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
February 2005
Figure 4–42. Regional Clocks
Fast Regional Clock Network
In EP1SGX25 and EP1SGX10 devices, there are two fast regional clock
networks, FCLK[1..0], within each quadrant, fed by input pins (see
Figure
networks within each half-quadrant (see
clocks can also be used for high fanout control signals, such as
asynchronous clears, presets, clock enables, or protocol control signals
such as TRDY and IRDY for PCI. Dual-purpose FCLK pins drive the fast
clock networks. All devices have eight FCLK pins to drive fast regional
clock networks. Any I/O pin can drive a clock or control signal onto any
fast regional clock network with the addition of a delay. The I/O
interconnect drives this signal.
RCLK[1..0]
RCLK[3..2]
CLK[3..0]
4–43). In EP1SGX40 devices, there are two fast regional clock
RCLK[15..14]
RCLK[5..4]
CLK[7..4]
Stratix GX Device Handbook, Volume 1
RCLK[13..12]
RCLK[7..6]
CLK[15..12]
Figure
Regional Clocks Only Drive a Device
Quadrant from Specified CLK Pins,
Recovered Clocks, or PLLs within
that Quadrant
4–44). The FCLK[1..0]
Stratix GX Architecture
Transceiver
Clocks
RCLK[11..10]
RCLK[9..8]
4–71