ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 97

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
February 2005
The read and write operation of the memory is controlled by the WREN
signal, which sets the ports into either read or write modes. There is no
separate read enable (RE) signal.
Writing into RAM is controlled by both the WREN and byte enable
(byteena) signals for each port. The default value for the byteena
signal is high, in which case writing is controlled only by the WREN signal.
The byte enables are available for the ×18, ×36, and ×72 modes. In the
×144 simple dual-port mode, the two sets of byteena signals
(byteena_a and byteena_b) are combined to form the necessary
16 byte enables.
64K
32K
16K
8K
Table 4–8. M-RAM Block Configurations (True Dual-Port)
Table 4–9. Byte Enable for M-RAM Blocks
byteena[3..0]
×
×
×
×
72
[0] = 1
[1] = 1
[2] = 1
[3] = 1
[4] = 1
[5] = 1
[6] = 1
[7] = 1
9
18
36
Port A
Tables 4–9
datain ×18
[17..9]
64K × 9
[8..0]
–
–
–
–
–
–
v
v
v
v
and
4–10
Stratix GX Device Handbook, Volume 1
summarize the byte selection.
32K × 18
v
v
v
v
Notes
datain ×36
[26..18]
[35..27]
[17..9]
[8..0]
Port B
–
–
–
–
(1),
16K × 36
(2)
Stratix GX Architecture
v
v
v
v
datain ×72
[26..18]
[35..27]
[44..36]
[53..45]
[62..54]
[71..63]
[17..9]
[8..0]
8K × 72
v
v
v
v
4–31