ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 165

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

Figure 4–60. Column I/O Block Connection to the Interconnect
Notes to
(1)
(2)
Altera Corporation
February 2005
The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0],
four clocks io_bclk[3..0], and four clear signals io_bclr[3..0].
The 42 data and control signals consist of 12 data out lines; six lines each for DDR applications
io_dataouta[5..0] and io_dataoutb[5..0], six output enables io_coe[5..0], six input clock enables
io_cce_in[5..0], six output clock enables io_cce_out[5..0], six clocks io_cclk[5..0], and six clear
signals io_cclr[5..0].
Figure
Local Interconnect
Signals from I/O
Interconnect (1)
from Logic Array (2)
R4, R8 & R24
Interconnects
4–60:
16 Control
I/O Block
Control Signals
42 Data &
Interconnect
LAB
LAB Local
16
Vertical I/O Block
Interconnects
C4, C8 & C16
42
LAB
Stratix GX Device Handbook, Volume 1
IO_datain[3:0]
LAB
Stratix GX Architecture
Vertical I/O
Block Contains
up to Six IOEs
io_clk[7..0]
I/O Interconnect
4–99