xc5210 Xilinx Corp., xc5210 Datasheet - Page 10

• Manufacturer Part Number: xc5210
• Description: Logic Cell Array Family , Inc
• Manufacturer: Xilinx Corp.

XC5200 Logic Cell Array Family
Development System
The powerful features of the XC5200 device family require
an equally powerful, yet easy-to-use, set of development
tools. Xilinx provides an enhanced version of the Xilinx
Automatic CAE Tools (XACT), optimized for the XC5200
family.
As with other logic technologies, the basic methodology
for XC5200 FPGA design consists of three interrelated
steps: design entry, implementation, and verification.
Popular generic tools are used for entry and simulation
(for example, Viewlogic Systems’s Viewdraw schematic
editor and Viewsim simulator), but architecture-specific
tools are needed for implementation.
All Xilinx development system software is integrated under
the Xilinx Design Manager (XDM™), providing designers
with a common user interface regardless of their choices
of entry and verification tools. XDM simplifies the selection
of command-line options with pull-down menus and online
help text. Application programs ranging from schematic
capture to Partitioning, Placement, and Routing (PPR)
can be accessed from XDM, while the program-command
sequence is generated and stored for documentation prior
to execution. The XMAKE command, a design compilation
utility, automates the entire implementation process,
automatically retrieving the design’s input files and
performing all the steps needed to create configuration
and report files.
Several advanced features of the XACT system facilitate
XC5200 FPGA design. RPMs — schematic-based macros
with relative location constraints to guide their placement
within the FPGA — help to ensure an optimized
implementation
abundance of local routing permits RPMs to be contained
within a single VersaBlock or to span across multiple
VersaBlocks. XACT-Performance allows designers to
enter the exact performance requirements during design
entry, at the schematic level, to guide PPR.
Design Entry
Designs can be entered graphically, using schematic-
capture software, or in any of several text-based formats
(such as Boolean equations, state-machine descriptions,
and high-level design languages).
Xilinx and third-party CAE vendors have developed library
and interface products compatible with a wide variety of
design-entry and simulation environments. A standard
interface-file specification, Xilinx Netlist File (XNF), is
provided to simplify file transfers into and out of the XACT
development system.
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Xilinx offers XACT development system interfaces to the
following design environments:
• Viewlogic Systems (Viewdraw, Viewsim)
• Mentor Graphics V8 (NETED, QuickSim, Design
• OrCAD (SDT, VST)
• Synopsys (Design Compiler, FPGA Compiler)
• Xilinx-ABEL (State Machine module generator)
• X-BLOX (Graphical Mode Generator)
Many other environments are supported by third-party
vendors. Currently, more than 100 packages are
supported.
The unified schematic library for the XC5200 FPGA
reflects the wide variety of logic functions that can be
implemented in these versatile devices. The library
contains over 400 primitives and macros, ranging from 2-
input AND gates to 16-bit accumulators, and includes
arithmetic
registers, decoders, encoders, I/O functions, latches,
Boolean functions, multiplexers, shift registers, and barrel
shifters.
Designing with macros is as easy as designing with
standard SSI/MSI functions. The “soft macro” library
contains detailed descriptions of common logic functions,
but does not contain any partitioning or routing
information. The performance of these macros depends,
therefore, on how the PPR software processes the design.
RPMs, on the other hand, do contain predetermined
partitioning and relative placement information, resulting
in an optimized implementation for these functions. Users
can create their own library elements — either soft macros
or RPMs — based on the macros and primitives of the
standard library.
The X-BLOX design language is a graphics-based high-
level description language (HDL) that allows designers to
use a schematic editor to enter designs as a set of generic
modules.
optimizes the modules for the target device architecture,
automatically choosing the appropriate architectural
resources for each function.
The XACT design environment supports hierarchical
design entry, with top-level drawings defining the major
functional blocks, and lower-level descriptions defining the
logic
automatically combine the hierarchical elements of a
design. Different hierarchical elements can be specified
with different design entry tools, allowing the use of the
most convenient entry method for each portion of the
design.
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