xc5210 Xilinx Corp., xc5210 Datasheet - Page 15

• Manufacturer Part Number: xc5210
• Description: Logic Cell Array Family , Inc
• Manufacturer: Xilinx Corp.

3-State Buffers
The XC5200 family has four dedicated TBUFs per CLB.
The four buffers are individually configurable through four
configuration bits to operate as simple non-inverting
buffers or in 3-state mode. When in 3-state mode the
CLB’s output enable (TS) control signal drives the enable
to all four buffers (see Figure 8). Each TBUF can drive up
to two horizontal Longlines
Oscillator
The XC5200 oscillator (OSC52) divides the internal 16-
MHz clock or a user clock that is connected to the “C” pin.
The user then has the choice of dividing by 4, 16, 64, or
256 for the “OSC1” output and dividing by 2, 8, 32, 128,
1024, 4096, 16384, or 65536 for the “OSC2” output. The
division is specified via a “DIVIDEn_BY=x” attribute on the
symbol, where n=1 for OSC1, or n=2 for OSC2. The
OSC5 macro is used where an internal oscillator is
required. The CK_DIV macro is applicable when a user
clock input is specified (see Figure 9).
Figure 8.
Figure 9.
Horizontal
Longlines
TS
CLB
CLB
LC3
LC2
LC1
LC0
XC5200 3-State Buffer
XC5200 Oscillator Macros
CLK
CK_DIV
OSC5
OSC1
OSC2
OSC1
OSC2
X5706
11
Start-Up
On start-up, all XC5200 internal flip-flops are reset. The
XC5200 devices do not support the “INIT=” attribute.
Thus, the XC5200 family has only a global reset (GR)
signal. The user can assign the pin location for the GR
signal and use it to reset asynchronously all of the flip-
flops in the design without using general routing
resources. The user can also assign a positive or negative
polarity to GR.
Boundary Scan
XC5200 devices support all the mandatory boundary-scan
instructions specified in the IEEE standard 1149.1. A Test
Access Port (TAP) and registers are provided that
implement
BYPASS instructions. The TAP can also support two
USERCODE instructions.
Boundary-scan operation is independent of individual IOB
configuration and package type. All IOBs are treated as
independently controlled bidirectional pins, including any
unbonded IOBs. Retaining the bidirectional test capability
after configuration provides flexibility for interconnect
testing.
Also, internal signals can be captured during EXTEST by
connecting them to unbonded IOBs, or to the unused
outputs in IOBs used as unidirectional input pins. This
technique partially compensates for the lack of INTEST
support.
The public boundary-scan instructions are always
available prior to configuration. After configuration, the
public instructions and any USERCODE instructions are
only available if specified in the design. While SAMPLE
and BYPASS are available during configuration, it is
recommended that boundary-scan operations not be
performed during this transitory period.
In addition to the test instructions outlined above, the
boundary-scan circuitry can be used to configure the
Logic Cell Array (LCA™) device, and to read back the
configuration data.
All of the XC4000 boundary-scan modes are supported in
the XC5200 family. Three additional outputs for the User
Register are provided (Reset, Update, and Shift),
representing the decoding of the corresponding state of
the boundary-scan internal state machine. For details on
boundary scan, refer to “Boundary Scan in XC4000
Devices — Application Note” on pages 8-45 through 8-42
of the 1994 Xilinx Programmable Logic Data Book.
the
EXTEST,
SAMPLE/PRELOAD,
and
R