xc5210 Xilinx Corp., xc5210 Datasheet - Page 25

• Manufacturer Part Number: xc5210
• Description: Logic Cell Array Family , Inc
• Manufacturer: Xilinx Corp.

Clear Address Registers
During this phase the configuration address registers are
cleared to ensure that they will contain at most a single
token at all times. Prior to memory initialization, the
XC5200 device eliminates the possibility of multiple
tokens within the address register, as is typically the case
when powering on.
Power-On Time-Out
An internal power-on reset circuit is triggered when power
is applied. When V
portions of the LCA begin to operate (i.e., performs a
write-and-read test of a sample pair of configuration
memory bits), the programmable I/O buffers are 3-stated
with active high-impedance pull-up resistors. A time-out
delay — nominally 4 ms — is initiated to allow the power-
supply voltage to stabilize. For correct operation the
power supply must reach V
out, and must not dip below it thereafter.
There is no distinction between master and slave modes
with regard to the time-out delay. Instead, the INIT line is
used to ensure that all daisy-chained devices have
completed initialization. Since XC2000 devices do not
have this signal, extra care must be taken to guarantee
proper operation when daisy-chaining them with XC5200
devices. For proper operation with XC3000 devices, the
RESET signal, which is used in XC3000 to delay
configuration, should be connected to INIT.
If the time-out delay is insufficient, configuration should be
delayed by holding the INIT pin Low until the power supply
has reached operating levels.
During all three phases — Power-on, Initialization, and
Configuration — DONE is held Low; HDC, LDC, and INIT
are active; DOUT is driven; and all I/O buffers are
disabled.
Initialization
This phase clears the configuration memory and
establishes the configuration mode.
The configuration memory is cleared at the rate of one
frame per internal clock cycle (nominally 1 MHz). An open-
drain bidirectional signal, INIT, is released when the
configuration memory is completely cleared. The device
then tests for the absence of an external active-low level
on INIT. The mode lines are sampled two internal clock
cycles later (nominally 2 s).
The master device waits an additional 32 s to 256 s
(nominally 64-128 s) to provide adequate time for all of
the slave devices to recognize the release of INIT as well.
Then the master device enters the Configuration phase.
CC
reaches the voltage at which
CC
(min) by the end of the time-
21
Configuration
The length counter begins counting immediately upon
entry into the configuration state. In slave-mode operation
it is important to wait at least two cycles of the internal
1-MHz clock oscillator after INIT is recognized before
toggling
Configuration will not begin until the internal configuration
logic reset is released, which happens two cycles after
INIT goes High. A master device’s configuration is
delayed from 32 to 256 s to ensure proper operation with
any slave devices driven by the master device.
A preamble field at the beginning of the configuration data
stream indicates that the next 24 bits represent the length
count. The length count equals the total number of
configuration
configuration data to all daisy-chained devices. Once the
preamble and length-count values have been passed
through to the next device in the daisy-chain, DOUT is
held High to prevent start bits from reaching any daisy-
chained devices. After fully configuring itself, the device
passes serial data to downstream daisy-chained devices
via DOUT until the full length count is reached.
Errors in the configuration bitstream are checked at the
end of a frame of data. The device does not check the
preamble or length count for errors. In a daisy-chained
configuration, configuration data for downstream devices
are not checked for errors. If an error is detected after
reading a frame, the ERR pin (also known as INIT) is
immediately pulled Low and all configuration activity
ceases. However, a master or Peripheral Asynchronous
device will continue outputting a configuration clock and
incrementing the PROM address indefinitely even though
it will never complete configuration. A reprogram or
power-on must be applied to remove the device from this
state.
Start-Up and Operation
The XC5200 start-up sequence is identical to that of the
XC4000 family. Each of these events may occur in any
order: (a) DONE is pulled High; and/or (b) user I/Os
become active; and/or (c) Internal Reset is deactivated.
As a configuration option, the three events may be
triggered by a user clock rather than by CCLK, or the start-
up sequence may be delayed by externally holding the
DONE pin Low.
In any mode, the clock cycles of the start-up sequence
hare not included in the length count. The length of the
bitstream is greater than the length count.
CCLK
bits
and
needed
feeding
to
the
load
serial
the
bitstream.
complete
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