xc5210 Xilinx Corp., xc5210 Datasheet - Page 14

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xc5210

Manufacturer Part Number
xc5210
Description
Logic Cell Array Family , Inc
Manufacturer
Xilinx Corp.
Datasheet

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XC5200 Logic Cell Array Family
Cascade Function
Each CY_MUX can be connected to the CY_MUX in the
adjacent LC to provide cascadable decode logic. Figure 7
illustrates how the 4-input function generators can be
configured to take advantage of these four cascaded
Figure 7.
XC5200 CY_MUX Used for Decoder Cascade Logic
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DI
DI
DI
DI
F4
F3
F2
F1
F4
F3
F2
F1
F4
F3
F2
F1
F4
F3
F2
F1
F=0
AND
AND
AND
AND
CI
cascade out
CY_MUX
CO
Initialization of
carry chain (One Logic Cell)
cascade in
CY_MUX
CY_MUX
CY_MUX
CY_MUX
10
CY_MUXes. Note that AND and OR cascading are
specific cases of a general decode. In AND cascading all
bits are decoded equal to logic one, while in OR
cascading all bits are decoded equal to logic zero. The
flexibility of the LUT achieves this result.
CE
CK
CLR
D
D
D
D
FD
FD
FD
FD
LC2
LC1
LC0
LC3
DO
DO
DO
DO
Q
Q
X
Q
X
X
X
Q
X5708
out
Preliminary (v1.0)

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