mc68hc912bc32 Freescale Semiconductor, Inc, mc68hc912bc32 Datasheet - Page 215

• Manufacturer Part Number: mc68hc912bc32
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

15.4.1 Power Off Mode
For guaranteed BDLC operation, this mode is entered from reset mode when the BDLC supply voltage,
V
(LVR) before being powered down. In power off mode, the pin input and output specifications are not
guaranteed.
15.4.2 Reset Mode
This mode is entered from power off mode when the BDLC supply voltage, V
specified value (V
asserted while powering up the BDLC or an unknown state is entered and correct operation cannot be
guaranteed. Reset mode is also entered from any other mode when any reset source is asserted.
In reset mode, the internal BDLC voltage references are operative, V
which are held in their reset state, and the internal BDLC system clock is running. Registers assume their
reset condition. Because outputs are held in their programmed reset state, inputs and network activity are
ignored.
15.4.3 Run Mode
This mode is entered from reset mode after all MCU reset sources are no longer asserted. Run mode is
entered from the BDLC wait mode when activity is sensed on the J1850 bus.
Run mode is entered from the BDLC stop mode when network activity is sensed, although messages are
not received properly until the clocks have stabilized and the CPU is also in run mode.
In this mode, normal network operation takes place. Ensure that all BDLC transmissions have ceased
before exiting this mode.
15.5 Power-Conserving Modes
The BDLC has three power-conserving modes:
Depending upon the logic level of the WCM bit in BDLC control register 1 (BCR1), the BDLC enters a
power-conserving mode when the CPU executes the STOP or WAIT instruction.
When a power-conserving mode is entered, any activity on the J1850 network causes the BDLC to exit
low-power mode. When exiting from BDLC stop mode, the BDLC generates an unmaskable interrupt of
the CPU. This wakeup interrupt state is reflected in the BDLC state vector register (BSVR) and encoded
as the highest priority interrupt.
Wait mode or stop mode does not reset the BDLC registers upon BDLC wakeup.
Freescale Semiconductor
DD
1. BDLC wait and CPU wait mode
2. BDLC stop and CPU wait mode
3. BDLC stop and CPU stop mode
, drops below its minimum specified value. The BDLC is placed in reset mode by low-voltage reset
DD
–10%) and an MCU reset source is asserted. The internal MCU reset must be
M68HC12B Family Data Sheet, Rev. 9.1
DD
is supplied to the internal circuits
DD
, rises above its minimum
Power-Conserving Modes
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