mc68hc912bc32 Freescale Semiconductor, Inc, mc68hc912bc32 Datasheet - Page 72

• Manufacturer Part Number: mc68hc912bc32
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Resets and Interrupts
4.6.4 Clock Monitor Reset
If clock frequency falls below a predetermined limit when the clock monitor is enabled, a reset occurs.
4.7 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known startup states, as described
here.
4.7.1 Operating Mode and Memory Map
The states of the BKGD, MODA, and MODB pins during reset determine the operating mode and default
memory mapping. The SMODN, MODA, and MODB bits in the MODE register reflect the status of the
mode-select inputs at the rising edge of reset. Operating mode and default maps can subsequently be
changed according to strictly defined rules.
4.7.2 Clock and Watchdog Control Logic
Reset enables the COP watchdog with the CR2–CR0 bits set for the shortest timeout period. The clock
monitor is disabled. The RTIF flag is cleared and automatic hardware interrupts are masked. The rate
control bits are cleared and must be initialized before the return-from-interrupt (RTI) system is used. The
DLY control bit is set to specify an oscillator startup delay upon recovery from stop mode.
4.7.3 Interrupts
Reset initializes the HPRIO register with the value $F2, causing the IRQ pin to have the highest I-bit
interrupt priority. The IRQ pin is configured for level-sensitive operation (for wired-OR systems). However,
the I and X bits in the CCR are set, masking IRQ and XIRQ interrupt requests.
4.7.4 Parallel Input/Output (I/O)
If the MCU comes out of reset in an expanded mode, port A and port B are the multiplexed address/data
bus. Port E pins are normally used to control the external bus. The port E assignment register (PEAR)
affects port E pin operation.
If the MCU comes out of reset in a single-chip mode, all ports are configured as general-purpose
high-impedance inputs.
4.7.5 Central Processing Unit (CPU)
After reset, the CPU fetches a vector from the appropriate address and begins executing instructions. The
stack pointer and other CPU registers are indeterminate immediately after reset. The condition code
register (CCR) X and I interrupt mask bits are set to mask any interrupt requests. The S bit is also set to
inhibit the STOP instruction.
4.7.6 Memory
After reset, the internal register block is located at $0000–$01FF, the register-following space is at
$0200–$03FF, and RAM is at $0800–$0BFF. EEPROM is located at $0D00–$0FFF. FLASH
EEPROM/ROM is located at $8000–$FFFF in single-chip modes and at $0000–$7FFF (but disabled) in
expanded modes.
M68HC12B Family Data Sheet, Rev. 9.1
72
Freescale Semiconductor