mc68hc912bc32 Freescale Semiconductor, Inc, mc68hc912bc32 Datasheet - Page 218

• Manufacturer Part Number: mc68hc912bc32
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Byte Data Link Communications (BDLC)
15.7 BDLC MUX Interface
The MUX (multiplex) interface is responsible for bit encoding/decoding and digital noise filtering between
the protocol handler and the physical interface.
15.7.1 Rx Digital Filter
The receiver section of the BDLC includes a digital low-pass filter to remove narrow noise pulses from the
incoming message. An outline of the digital filter is shown in
Figure
15-3.
DATA
INPUT
4-BIT UP/DOWN COUNTER
LATCH
SYNC
RX DATA
FILTERED
FROM
RX DATA OUT
PHYSICAL
D
Q
UP/DOWN
OUT
D
Q
INTERFACE
(BDRXD)
MUX
INTERFACE
CLOCK
Figure 15-3. BDLC Rx Digital Filter Block Diagram
15.7.1.1 Operation
The clock for the digital filter is provided by the MUX interface clock (see f
parameter in
Table
15-2).
BDLC
At each positive edge of the clock signal, the current state of the receiver physical interface (BDRxD)
signal is sampled. The BDRxD signal state is used to determine whether the counter should increment or
decrement at the next negative edge of the clock signal.
The counter increments if the input data sample is high but decrements if the input sample is low.
Therefore, the counter progresses either up toward 15 if, on average, the BDRxD signal remains high or
progresses down toward 0 if, on average, the BDRxD signal remains low.
When the counter eventually reaches the value 15, the digital filter decides that the condition of the
BDRxD signal is at a stable logic level 1 and the data latch is set, causing the filtered Rx data signal to
become a logic level 1. Furthermore, the counter is prevented from overflowing and can be decremented
only from this state.
Alternatively, should the counter eventually reach the value 0, the digital filter decides that the condition
of the BDRxD signal is at a stable logic level 0 and the data latch is reset, causing the filtered Rx data
signal to become a logic level 0. Furthermore, the counter is prevented from underflowing and can be
incremented only from this state.
The data latch retains its value until the counter next reaches the opposite end point, signifying a definite
transition of the signal.
M68HC12B Family Data Sheet, Rev. 9.1
218
Freescale Semiconductor