mc68hc11c0 Freescale Semiconductor, Inc, mc68hc11c0 Datasheet - Page 36

• Manufacturer Part Number: mc68hc11c0
• Description: 8-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

6 Resets and Interrupts
36
MOTOROLA
The MC68HC11C0 has three reset vectors and 18 interrupt vectors. The reset vectors are as follows:
The 18 interrupt vectors service 30 interrupt sources (three non-maskable, 27 maskable). The three
non-maskable interrupt vectors are as follows:
On-chip peripheral systems generate maskable interrupts, which are recognized only if the global inter-
rupt mask bit (I) in the condition code register (CCR) is clear. Maskable interrupts are prioritized accord-
ing to a default arrangement; however, any one source can be elevated to the highest maskable priority
position by a software-accessible control register, HPRIO. The HPRIO register can be written at any
time, provided the I bit in the CCR is set.
Twenty-seven interrupt sources in the MC68HC11C0 are subject to masking by a global interrupt mask
bit (I bit in the CCR). In addition to the global I bit, all of these sources are controlled by local enable bits
in control registers. Most interrupt sources in M68HC11 devices have separate interrupt vectors; there-
fore, it is not usually necessary for software to poll control registers to determine the cause of an inter-
rupt. In the case of the keyboard interrupt inputs, software must poll the port F interrupt status register
(FISTAT) immediately following an interrupt to determine its source.
For some interrupt sources, such as the SCI and keyboard interrupts, flags are automatically cleared
during the normal course of responding to the interrupt requests. For example, the RDRF flag in the SCI
system is cleared by an automatic clearing mechanism consisting of a read of the SCI status register
while RDRF is set, followed by a read of the SCI data register. The normal response to an RDRF inter-
rupt request would be to read the SCI status register to check for receive errors, then to read the re-
ceived data from the SCI data register. These two steps satisfy the automatic clearing mechanism
without requiring any special instructions. Similarly, port F interrupt status register (FISTAT) is cleared
when the CPU reads the register to determine which input was the source of the interrupt.
Refer to the following table for interrupt and reset vector assignments.
• RESET, or Power-On Reset
• Clock Monitor Fail
• COP Failure
• XIRQ Pin (X-Bit Interrupt)
• Illegal Opcode Trap
• Software Interrupt
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MC68HC11C0TS/D
MC68HC11C0